Abstract:
A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.
Abstract:
Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.
Abstract:
A capacitor structure includes a plurality of lower electrodes, a support pattern structure, a dielectric layer, and an upper electrode. The lower electrodes are formed on a substrate. The support pattern structure is formed between the lower electrodes, and includes a lower support pattern and an upper support pattern structure over the lower support pattern. The upper support pattern structure includes a plurality of upper support patterns spaced apart from each other in a direction substantially perpendicular to a top surface of the substrate. The dielectric layer is formed on the lower electrodes and the support pattern structure. The upper electrode is formed on the dielectric layer. A sum of thicknesses of the plurality of upper support patterns in the direction substantially perpendicular to the top surface of the substrate is about 35% to about 85% of a total thickness of the upper support pattern structure.