公开(公告)号：US20230164979A1

公开(公告)日：2023-05-25

申请号：US17931880

申请日：2022-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Park ,  Hanjin Lim

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885

Abstract: A semiconductor device includes a first contact plug on a substrate, a capacitor, an insulating division layer, and a second contact plug. The capacitor includes first and second electrodes and a dielectric layer. The first electrode contacts an upper surface of the first contact plug, and extends in a vertical direction substantially perpendicular to an upper surface of the substrate. The second electrode is spaced apart from the first electrode, and extends in the vertical direction and includes lower and upper surfaces substantially coplanar with lower and upper surfaces, respectively, of the first electrode. The dielectric layer is on sidewalls of the first and second electrodes. The insulating division layer is formed between portions of the dielectric layer on the sidewalls of the first and second electrodes. The second contact plug contacts the upper surface of the second electrode.

公开(公告)号：US20200350256A1

公开(公告)日：2020-11-05

申请号：US16933544

申请日：2020-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok Lee ,  Hyeonjin Shin ,  Seongjun Park ,  Donghyun Im ,  Hyun Park ,  Keunwook Shin ,  Jongmyeong Lee ,  Hanjin Lim

IPC: H01L23/532

Abstract: Example embodiments relate to a wiring structure, a method of forming the same, and an electronic device employing the same. The wiring structure includes a first conductive material layer and a nanocrystalline graphene layer on the first conductive material layer in direct contact with the metal layer.

公开(公告)号：US12199138B2

公开(公告)日：2025-01-14

申请号：US17941688

申请日：2022-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak Jeon ,  Jiye Baek ,  Hanjin Lim

IPC: H10B12/00 ,  H01L49/02

Abstract: A semiconductor device of the disclosure may include a substrate, a gate structure on the substrate, a capacitor contact structure connected to the substrate, a lower electrode connected to the capacitor contact structure, a supporter supporting a sidewall of the lower electrode, an interfacial layer covering the lower electrode and including a halogen material, a capacitor insulating layer covering the interfacial layer and the supporter, and an upper electrode covering the capacitor insulating layer. The interfacial layer may include a first surface contacting the lower electrode, and a second surface contacting the capacitor insulating layer. The halogen material of the interfacial layer may be closer to the first surface than to the second surface.

公开(公告)号：US20240404947A1

公开(公告)日：2024-12-05

申请号：US18673201

申请日：2024-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Hanjin Lim ,  Jinwoo Han

IPC: H01L23/528 ,  H10B12/00

Abstract: A semiconductor device includes: cell transistors stacked in a first direction perpendicular to an upper surface of a base, wherein each cell transistor includes a first source/drain region, a second source/drain region, and a gate electrode, a bit line extending in the first direction and electrically connected to the first source/drain regions; and data storage structures electrically connected to the second source/drain regions, wherein each gate electrode has a line shape extending in a second direction parallel to the upper surface, each data storage structure includes a first electrode, a second electrode, and a dielectric layer between the first and second electrodes, wherein the first electrodes are electrically connected to the second source/drain regions, wherein the second electrodes are stacked and spaced apart from each other in the first direction, and wherein each second electrode includes a line portion having a line shape extending in the second direction.

公开(公告)号：US20240357801A1

公开(公告)日：2024-10-24

申请号：US18530342

申请日：2023-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanjin Lim ,  Jinwoo Han ,  Kiseok Lee ,  Keunnam Kim ,  Seokhan Park ,  Moonyoung Jeong

IPC: H10B12/00 ,  H01L21/28 ,  H01L29/51

CPC classification number: H10B12/482 ,  H01L29/40111 ,  H01L29/516 ,  H10B12/315 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor memory device includes a bit line extending in a first direction, an active pattern on the bit line, the active pattern including first and second vertical portions facing each other in the first direction and a horizontal portion connecting the first and second vertical portions, first and second word lines on the horizontal portion between the first and second vertical portions, the first and second word lines extending in a second direction crossing the first direction, a gate insulating pattern between the first and second word lines and the active pattern, and a capacitor connected to each of the first and second vertical portions, the capacitor including a first electrode pattern connected to one of the first and second vertical portions, a second electrode pattern on the first electrode pattern, and a ferroelectric pattern between the first electrode pattern and the second electrode pattern.

公开(公告)号：US11978704B2

公开(公告)日：2024-05-07

申请号：US16933544

申请日：2020-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok Lee ,  Hyeonjin Shin ,  Seongjun Park ,  Donghyun Im ,  Hyun Park ,  Keunwook Shin ,  Jongmyeong Lee ,  Hanjin Lim

IPC: H01L23/532

CPC classification number: H01L23/53276 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Example embodiments relate to a wiring structure, a method of forming the same, and an electronic device employing the same. The wiring structure includes a first conductive material layer and a nanocrystalline graphene layer on the first conductive material layer in direct contact with the metal layer.

公开(公告)号：US20240090200A1

公开(公告)日：2024-03-14

申请号：US18326145

申请日：2023-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hanjin Lim ,  Jungmin Park

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/34

Abstract: An integrated circuit device includes a transistor on a substrate and a capacitor structure electrically connected to the transistor, wherein the capacitor structure includes a first electrode including a first conductive material having a first work function, a dielectric layer on the first electrode, the dielectric layer including first metal, a second electrode on the first electrode with the dielectric layer therebetween and including a second conductive material having a second work function that is less than the first work function, and an interfacial layer between the dielectric layer and the second electrode, where an electrical energy barrier between the second electrode and the dielectric layer is increased by the interfacial layer relative to that of a direct interface therebetween.

公开(公告)号：US20230363142A1

公开(公告)日：2023-11-09

申请号：US18130769

申请日：2023-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak Jeon ,  Hanjin Lim ,  Hyungsuk Jung

IPC: H10B12/00

CPC classification number: H10B12/31 ,  H10B12/033

Abstract: A semiconductor memory device includes an interlayer insulating layer, a plurality of first contact pads embedded in the interlayer insulating layer, a plurality of first work function adjustment patterns embedded in the interlayer insulating layer and disposed on the plurality of first contact pads, and a plurality of lower electrodes disposed on the plurality of first work function adjustment patterns.

公开(公告)号：US20230290810A1

公开(公告)日：2023-09-14

申请号：US18050967

申请日：2022-10-28

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： JUNGMIN PARK ,  Hanjin Lim ,  Hyungsuk JUNG

IPC: H01L21/02

CPC classification number: H01L28/56 ,  H01L27/11507 ,  H01L27/11504

Abstract: A semiconductor device includes a capacitor structure. The capacitor structure includes a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked in a first direction. The dielectric layer includes first dielectric layers and second dielectric layers interposed between the bottom electrode and the top electrode and are that are alternately stacked in the first direction. The first dielectric layers include a ferroelectric material, and the second dielectric layers include an anti-ferroelectric material. A lowermost second dielectric layer is interposed between a lowermost first dielectric layer and the bottom electrode, and an uppermost second dielectric layer is interposed between an uppermost first dielectric layer and the top electrode.

公开(公告)号：US20230117391A1

公开(公告)日：2023-04-20

申请号：US17844623

申请日：2022-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak Jeon ,  Hyukwoo Kwon ,  Hanjin Lim

IPC: H01L27/108

Abstract: An integrated circuit semiconductor device includes a lower electrode formed on a substrate extending in a first direction and a second direction perpendicular to the first direction and a support structure supporting the lower electrode. The support structure includes a support pattern surrounding the lower electrode, extending in the first direction and the second direction, and having a hole through which the lower electrode passes, and a concavo-convex structure having at a surface of the support pattern a plurality of convex portions extending in a third direction perpendicular to the first direction and the second direction, and a plurality of concave portions arranged between the convex portions.