公开(公告)号：US12069849B2

公开(公告)日：2024-08-20

申请号：US18124043

申请日：2023-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Taejin Park ,  Yoosang Hwang

IPC: H10B12/00 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H10B12/482 ,  H01L21/3213 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/823468 ,  H01L29/6656 ,  H10B12/033 ,  H10B12/053 ,  H10B12/31 ,  H10B12/315 ,  H10B12/34

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

公开(公告)号：US11610896B2

公开(公告)日：2023-03-21

申请号：US17245203

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Taejin Park ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L21/768 ,  H01L29/66 ,  H01L21/3213

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

公开(公告)号：US11088148B2

公开(公告)日：2021-08-10

申请号：US16509820

申请日：2019-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeik Kim ,  Semyeong Jang ,  Jemin Park ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/792 ,  H01L21/71 ,  H01L21/8234

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US10978397B2

公开(公告)日：2021-04-13

申请号：US16707294

申请日：2019-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L21/764 ,  H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L27/24

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

公开(公告)号：US10535605B2

公开(公告)日：2020-01-14

申请号：US15782556

申请日：2017-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L21/764 ,  H01L23/522 ,  H01L23/528 ,  H01L27/108 ,  H01L27/24

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

公开(公告)号：US20180286870A1

公开(公告)日：2018-10-04

申请号：US15845141

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Semyeong Jang ,  Jemin Park ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L29/792 ,  H01L21/28 ,  H01L21/71

CPC classification number: H01L27/10885 ,  H01L21/28273 ,  H01L21/71 ,  H01L21/823475 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10882 ,  H01L29/40114 ,  H01L29/7926

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US09929013B2

公开(公告)日：2018-03-27

申请号：US15402545

申请日：2017-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Yoosang Hwang

IPC: H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L27/11531 ,  H01L27/11575

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include etching a bulk pattern on a peripheral region to form patterns and then forming a layer on both a cell region and a peripheral region. The methods may include forming line patterns that extend from the cell region onto the peripheral region and then forming a layer on both the cell region and a peripheral region.

公开(公告)号：US20180040561A1

公开(公告)日：2018-02-08

申请号：US15782556

申请日：2017-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L27/108 ,  H01L27/24

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.