One time programmable (OTP) low power circuits and methods for providing bias voltages to wordlines

    公开(公告)号:US12224023B2

    公开(公告)日:2025-02-11

    申请号:US17979051

    申请日:2022-11-02

    Abstract: Embodiments herein disclose an OTP low power circuit and methods for providing bias voltages using a single regulator. The circuit includes a Bitcell, a diode drop, a charge pump, a combinational logic controller, a program current sink load, and a read current sink load. The Bitcell includes programmable word lines and read lines, and is configured to operate in either a programmable mode or a read mode. The diode drop is configured to provide a second bias voltage to drive the read lines and the single regulator is configured to provide a first bias voltage to drive the WP in the read mode. The charge pump is configured to provide a third bias voltage to drive the WP in the program mode.

    ONE TIME PROGRAMMABLE (OTP) LOW POWER CIRCUITS AND METHODS FOR PROVIDING BIAS VOLTAGES TO WORDLINES

    公开(公告)号:US20240079070A1

    公开(公告)日:2024-03-07

    申请号:US17979051

    申请日:2022-11-02

    CPC classification number: G11C17/18 G11C17/16

    Abstract: Embodiments herein disclose an OTP low power circuit and methods for providing bias voltages using a single regulator. The circuit includes a Bitcell, a diode drop, a charge pump, a combinational logic controller, a program current sink load, and a read current sink load. The Bitcell includes programmable word lines and read lines, and is configured to operate in either a programmable mode or a read mode. The diode drop is configured to provide a second bias voltage to drive the read lines and the single regulator is configured to provide a first bias voltage to drive the WP in the read mode. The charge pump is configured to provide a third bias voltage to drive the WP in the program mode.

    BITLINE PRECHARGE SYSTEM FOR A SEMICONDUCTOR MEMORY DEVICE

    公开(公告)号:US20220366970A1

    公开(公告)日:2022-11-17

    申请号:US17815003

    申请日:2022-07-26

    Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device. Further, the at least one bitline is discharged from the precharge voltage (VDDM) level during at least one of the read operation or the write operation.

    CMOS-assisted inside-out dynamic vision sensor tracking for low power mobile platforms

    公开(公告)号:US11381741B2

    公开(公告)日:2022-07-05

    申请号:US16953111

    申请日:2020-11-19

    Abstract: An untethered apparatus for performing inside-out device tracking based on visual-inertial simultaneous location and mapping (SLAM) includes a dynamic vision sensor (DVS) configured to output an asynchronous stream of sensor event data, an inertial measurement unit (IMU) sensor configured to collect IMU data associated with motion of the apparatus at a predetermined interval, a processor and a memory. The memory contains instructions, which when executed by the processor, cause the apparatus to accumulate DVS sensor output over a sliding time window, the sliding time window including the predetermined interval, apply a motion correction to the accumulated DVS sensor output, the motion correction based on the IMU data collected over the predetermined interval, generate an event-frame histogram of DVS sensor events based on the motion correction, and provide the event-frame histogram of the DVS sensor events and the IMU data to a visual inertial SLAM pipeline.

    BITLINE PRECHARGE SYSTEM FOR A SEMICONDUCTOR MEMORY DEVICE

    公开(公告)号:US20220108744A1

    公开(公告)日:2022-04-07

    申请号:US16952712

    申请日:2020-11-19

    Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device. Further, the at least one bitline is discharged from the precharge voltage (VDDM) level during at least one of the read operation or the write operation.

    Semantic mapping for low-power augmented reality using dynamic vision sensor

    公开(公告)号:US10812711B2

    公开(公告)日:2020-10-20

    申请号:US16415860

    申请日:2019-05-17

    Abstract: An apparatus includes a dynamic vision sensor (DVS) configured to output an asynchronous stream of sensor event data, a CMOS image sensor configured to output frames of image data, an inertial measurement unit (IMU), a processor and a memory. The memory contains instructions, which when executed by the processor, cause the apparatus to generate a semantic segmentation of a time-stamped frame, which is based on one or more of an output of the CMOS image sensor, or a synthesized event frame based on an output from the DVS and an output from the IMU over a time interval. The semantic segmentation includes a semantic label associated with a region of the time-stamped frame. When executed, the instructions further cause the apparatus to determine, based on the semantic segmentation, a simplified object representation in a coordinate space, and update a stable semantic map based on the simplified object representation.

Patent Agency Ranking