公开(公告)号：US10204544B2

公开(公告)日：2019-02-12

申请号：US15350917

申请日：2016-11-14

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sung-Hwan Kim ,  Jun-Hyun Park ,  Kyoung-Ju Shin

IPC: G09G3/20 ,  G09G3/3266 ,  G11C19/28 ,  G09G3/3233

Abstract: A display panel driver includes a plurality of stages. An N-th stage of the plurality of stages is configured to output a scan signal and an emission signal synchronized with each other based on a first power voltage, a second power voltage, and at least one clock signal. N is a natural number.

公开(公告)号：US09947274B2

公开(公告)日：2018-04-17

申请号：US15299250

申请日：2016-10-20

Applicant: Samsung Display Co., Ltd.

Inventor： Jun-Hyun Park ,  Sung-Hwan Kim ,  Kyoung-Ju Shin ,  Sang-Uk Lim ,  Yang-Hwa Choi

IPC: G09G3/32 ,  G09G3/3266 ,  G09G3/3233 ,  G09G3/325 ,  G09G3/3291

CPC classification number: G09G3/3266 ,  G09G3/3233 ,  G09G3/325 ,  G09G3/3291 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0214 ,  G11C19/28

Abstract: A gate driver includes a plurality of stages outputting a plurality of gate output signals, respectively. Each stage includes a first input circuit applying an input signal to a first node in response to a first clock signal, a second input circuit applying the first clock signal to a second node in response to a voltage of the first node, a first output circuit controlling a gate output signal to a first logic level in response to the voltage of the first node, a second output circuit controlling the gate output signal to a second logic level in response to a voltage of the second node, and a leakage current blocking circuit applying a first power voltage corresponding to the first logic level to the first input circuit in response to the voltage of the first node.

公开(公告)号：US20170098422A1

公开(公告)日：2017-04-06

申请号：US15383686

申请日：2016-12-19

Applicant: Samsung Display Co., Ltd.

Inventor： Jae-Keun Lim ,  Ji-Sun Kim ,  Kyoung-Ju Shin ,  Chong-Chul Chai ,  Jong-Hee Kim

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0289 ,  G09G2310/06 ,  G09G2310/08 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2340/0435

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

公开(公告)号：US09524690B2

公开(公告)日：2016-12-20

申请号：US14461359

申请日：2014-08-15

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jae-Keun Lim ,  Ji-Sun Kim ,  Kyoung-Ju Shin ,  Chong-Chul Chai ,  Jong-Hee Kim

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0289 ,  G09G2310/06 ,  G09G2310/08 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2340/0435

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

Abstract translation: 门驱动电路包括：上拉控制器，响应于前一级之一的进位信号，将先前级之一的进位信号应用于第一节点; 输出时钟信号作为第N栅极输出信号的上拉部分; 输出时钟信号作为第N个进位信号的进位部分; 第一下拉部分，将第一节点处的信号下拉到第二关断电压; 第二下拉部分，将第N栅极输出信号下拉到第一关断电压; 反相部分基于时钟信号和第二截止电压产生反相信号，以将反相信号输出到反相节点; 以及将复位信号输出到反相节点的复位部分。

公开(公告)号：US09449562B2

公开(公告)日：2016-09-20

申请号：US15003189

申请日：2016-01-21

Applicant: Samsung Display Co., Ltd.

Inventor： Kyoung-Ju Shin ,  Chong-Chul Chai ,  Eun-Ju Kim

IPC: G09G3/34 ,  G09G3/20 ,  G02B26/04

CPC classification number: G09G3/3433 ,  G02B26/02 ,  G02B26/04 ,  G09G3/2007 ,  G09G3/2081 ,  G09G3/3466 ,  G09G5/10 ,  G09G2300/04 ,  G09G2300/0861 ,  G09G2310/0262 ,  G09G2310/08

Abstract: A display apparatus includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. Each pixel of the plurality of pixels comprises a switching device coupled to a corresponding gate line of the plurality of gate lines and to a corresponding data line of the plurality of data lines, a micro-electro-mechanical system coupled to an output electrode of the switching device, and a control device coupled to the output electrode of the switching device. The control device comprises a storage capacitor coupled to the output electrode of the switching device and a coupling capacitor coupled to the output electrode of the switching device, the storage capacitor connected in parallel with the coupling capacitor. The output electrode of the switching device, the storage capacitor, the coupling capacitor, and a first electrode of the micro-electro-mechanical system are all directly connected to each other.

Abstract translation: 显示装置包括多条栅极线，多条数据线和多个像素。 多个像素的每个像素包括耦合到多个栅极线中的相应栅极线和多个数据线的对应数据线的开关器件，耦合到该多个栅极线的输出电极的微电子机械系统 开关器件，以及耦合到开关器件的输出电极的控制器件。 控制装置包括耦合到开关装置的输出电极的存储电容器和耦合到开关装置的输出电极的耦合电容器，该存储电容器与耦合电容器并联连接。 开关器件的输出电极，存储电容器，耦合电容器以及微电子机械系统的第一电极都直接连接在一起。

公开(公告)号：US09088788B2

公开(公告)日：2015-07-21

申请号：US13844262

申请日：2013-03-15

Applicant: Samsung Display Co., LTD.

Inventor： Kyoung-Ju Shin ,  Jung-Won Kim ,  Cheol-Woo Park ,  Hee-Soon Jeong

IPC: G09G5/00 ,  H04N13/04 ,  G09G3/00 ,  G09G3/36 ,  H04N13/00

CPC classification number: H04N13/30 ,  G09G3/003 ,  G09G3/3648 ,  G09G2310/0283 ,  G09G2310/063 ,  G09G2320/0209 ,  G09G2320/0252 ,  G09G2320/0271 ,  G09G2320/0285 ,  G09G2340/0435 ,  G09G2340/16 ,  H04N13/111 ,  H04N13/139 ,  H04N13/337 ,  H04N13/341 ,  H04N13/398

Abstract: A method of displaying a three-dimensional image, the method includes sequentially displaying a first three-dimensional image on a plurality of horizontal lines of a display panel along a scan direction, and simultaneously displaying a black image on the horizontal lines of the display panel, the black image being inserted between the three-dimensional images having different images.

Abstract translation: 一种显示三维图像的方法，该方法包括：沿着扫描方向在显示面板的多个水平行上依次显示第一三维图像，并且同时在显示面板的水平线上显示黑色图像 黑色图像被插入在具有不同图像的三维图像之间。