公开(公告)号：US12028639B2

公开(公告)日：2024-07-02

申请号：US17649858

申请日：2022-02-03

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Nicolas Moeneclaey ,  Samuel Foulon

IPC: H04N25/778 ,  G01J1/42 ,  G01J1/44 ,  H04N25/772

CPC classification number: H04N25/778 ,  G01J1/4204 ,  G01J1/44 ,  H04N25/772

Abstract: A photosensitive device includes a peripheral circuit semiconductor region, a photosensitive circuit semiconductor region including at least one group of at least two photosensitive elements configured to generate a photoelectric signal on a node called critical node. The device further includes an integrator circuit per group of photosensitive elements, each including: a differential circuit for each photosensitive element of the group, in the photosensitive circuit semiconductor region, an amplification circuit, in the peripheral circuit semiconductor region, and a feedback circuit for each photosensitive element of the group, comprising a capacitive element located in the photosensitive circuit semiconductor region coupled between the output node of the amplification circuit and the respective critical node.

公开(公告)号：US11855654B2

公开(公告)日：2023-12-26

申请号：US17707113

申请日：2022-03-29

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics International N.V.

Inventor： Nicolas Moeneclaey ,  Sri Ram Gupta

IPC: H03M1/12 ,  H03M1/46

CPC classification number: H03M1/462 ,  H03M1/122 ,  H03M1/1245 ,  H03M1/468

Abstract: A successive approximation analog-to-digital converter includes a digital-to-analog converter DAC configured to receive a digital signal. First conversion units of the DAC are configured to sample an analog signal via a first switch and provide a first level voltage. Each first conversion unit includes a first capacitor array and a first switch array controlled from the digital signal. A single second conversion unit of the DAC is configured to provide a second level voltage. The second conversion unit includes a second capacitor array and a second switch array. A comparator operates to compare each of the first level voltages to the second level voltage and to provide a comparison signal based on each comparison and actuation of a set of third switches. A control circuit closes the first switches simultaneously and closes the third switches successively for the conversion of each sampled analog signal.

公开(公告)号：US20230154919A1

公开(公告)日：2023-05-18

申请号：US17969867

申请日：2022-10-20

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Nicolas Moeneclaey ,  Jean-Luc Patry

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0288 ,  H01L27/0262

Abstract: In embodiments, an integrated circuit is provided that includes an input/output cell having a first signal terminal and a second signal terminal connected to a domain and capable of withstanding a maximum voltage greater than the power supply voltage. The input/output cell further includes an array of N diodes coupled in series between the second signal terminal and a cold power supply point. The array has an overall threshold voltage greater than the maximum voltage. The integrated circuit further includes a control circuit connected between the first signal terminal and the array of diodes. The control circuit is configured, in the presence of a second voltage on the first signal terminal greater than the maximum voltage, to automatically and autonomously short-circuit at least one of the diodes in the array to limit the voltage on the second signal terminal to a third voltage less than the maximum voltage.

公开(公告)号：US20230045492A1

公开(公告)日：2023-02-09

申请号：US17963759

申请日：2022-10-11

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Samuel Rigault ,  Nicolas Moeneclaey ,  Xavier Branca

IPC: H01S5/042 ,  H01S5/068

Abstract: A driver circuit includes a fly capacitor with a first end and a second end. The driver circuit includes a laser diode having an anode and a cathode. The driver circuit is configured to operate in first and second operating states. The anode is coupled to the first end of the fly capacitor. In the first operating state, the cathode is coupled to a first voltage supply node, the first end of the fly capacitor is coupled to a second voltage supply node, and the second end of the fly capacitor is coupled to a first reference terminal. In the second operating state, the cathode is coupled to a second reference terminal and decoupled from the first voltage supply node, the first end of the fly capacitor is decoupled from the second voltage supply node, and the second end of the fly capacitor is coupled to a third reference terminal.

公开(公告)号：US11211770B2

公开(公告)日：2021-12-28

申请号：US16577103

申请日：2019-09-20

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Samuel Rigault ,  Nicolas Moeneclaey

IPC: H01S5/042 ,  H01S5/026 ,  H01S5/06

Abstract: A circuit includes a laser diode and a switched-capacitance charge pump coupled to control the laser diode. The charge pump can include a capacitor and a switching circuit that is capable of triggering a charge and discharge of the capacitor. The switching circuit can include a switch and an inverting circuit.

公开(公告)号：US10042000B2

公开(公告)日：2018-08-07

申请号：US15689237

申请日：2017-08-29

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Nicolas Moeneclaey

IPC: H03M1/50 ,  G01R31/3193 ,  G01R31/3187 ,  H04L7/00 ,  H03L7/18 ,  H03L7/085 ,  G01R31/317 ,  H03M1/12 ,  H03M1/00 ,  H04N5/335 ,  H04N3/14 ,  H01L27/146

Abstract: A method can be used to generate a reference clock signal having a reference frequency. N clock sub-signals are generated, where N is greater than or equal to 2. The N clock sub-signals are successively mutually shifted out of phase by π/N and each clock sub-signal has an elementary frequency that is equal to the reference frequency divided by N. The N clock sub-signals are propagated over propagation paths. The elementary frequency and a length of the longest propagation path are chosen so that each sub-signal has an acceptable degree of deformation. The duration of each sub-signal edge is longer than quarter of the period of the reference frequency. The reference clock signal is generated by EXCLUSIVE OR combining the propagated clock sub-signals at the end of their respective propagation paths.

公开(公告)号：US09807334B1

公开(公告)日：2017-10-31

申请号：US15492139

申请日：2017-04-20

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Nicolas Moeneclaey ,  Tarek Lule ,  Alexis Marcellin

IPC: H03M1/56 ,  H04N5/378 ,  H04N5/217 ,  H03M1/12 ,  H03M1/00 ,  H04N3/14 ,  H04N5/335

CPC classification number: H04N5/378 ,  H03M1/00 ,  H03M1/12 ,  H03M1/56 ,  H04N3/155 ,  H04N5/2173 ,  H04N5/335

Abstract: A device for conversion of an analog signal into a digital signal includes a clock signal generator and a ramp generator configured for delivering a rising voltage ramp. A comparator is configured for comparing the value of the analog signal and the value of the voltage ramp and for generating a comparison signal taking a first logical value when the two values are equal. A signal generator is configured for generating a counter signal equal to the inverse of the clock signal if the comparison signal takes its first value while the clock signal is in the high state, or a counter signal equal to the clock signal if the clock signal is in the low state. A counter is configured for counting the number of edges of the counter signal.