公开(公告)号：US20180026134A1

公开(公告)日：2018-01-25

申请号：US15649984

申请日：2017-07-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi EIKYU ,  Atsushi SAKAI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/28 ,  H01L29/08

CPC classification number: H01L29/7835 ,  H01L21/28061 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/402 ,  H01L29/42312 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/78624

Abstract: In an LDMOS having an element isolation region of an STI structure, there is prevented an occurrence of insulation breakdown which might be caused when electrons generated in a semiconductor substrate near an edge portion of a bottom face of the element isolation region are poured into a gate electrode. Immediately over an upper surface of an offset region adjacent to the element isolation region embedded in a main surface of the semiconductor substrate between a source region and a drain region, there is provided a trench penetrating a silicon film forming the gate electrode. As a consequence, the silicon film and a metal film for filling the trench form the gate electrode.