公开(公告)号：US09641077B2

公开(公告)日：2017-05-02

申请号：US14609203

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Chi-Fan Yung ,  Vishal Gupta ,  Joseph Duncan

IPC: H02M3/158 ,  H02M1/32 ,  H02M1/36 ,  H02M3/155 ,  G01R31/40

CPC classification number: H02M3/158 ,  G01R31/40 ,  H02M1/32 ,  H02M1/36 ,  H02M3/155

Abstract: Reliability of a buck power stage may be enhanced by extending the maximum input voltage able to be withstood in the disabled (non-switching) state. During device qualification/testing, a power management unit (PMU) in the disabled state may have its input node subjected to greater than a maximum input voltage permitted for reliability (Vmax). Under such conditions, a force voltage (Vforce) may be selectively applied to the PMU switching node in the disabled state. For a given input voltage (VIN), this reduces voltage across the non-switching transistors of the power stage (and hence the resulting stress) to below Vmax. In certain embodiments, the Vforce applied to the switching node is of a fixed magnitude. In other embodiments, the Vforce applied to the switching node is of a magnitude varying with input voltage. Embodiments may be particularly suited to implement power management for a System-On-Chip (SoC).

公开(公告)号：US09548739B2

公开(公告)日：2017-01-17

申请号：US14671553

申请日：2015-03-27

Applicant: QUALCOMM Incorporated

Inventor： Vishal Gupta ,  Chifan Yung ,  Joseph Duncan

IPC: H03K5/12 ,  H03K3/00 ,  H03K19/0185 ,  H03F3/217 ,  H03K17/10

CPC classification number: H03K19/018507 ,  H03F3/2173 ,  H03F2203/30015 ,  H03F2203/30084 ,  H03F2203/30099 ,  H03F2203/30117 ,  H03F2203/30132 ,  H03K17/102

Abstract: Disclosed is a cascode configuration that moves the gate of the cascode substantially without delay relative to an output node by capacitively coupling the latter onto the cascode gates. The passive coupling eliminates the need for actively driving the gates of the cascode. In some embodiments, the only circuitry needed on the cascode gate may be a biasing circuit that limits the swing on the cascode gate between Vmax and 2×Vmax, where Vmax is a transistor device rating.

Abstract translation: 公开了一种共源共栅结构，其通过将电容耦合到共源共栅电路上而相对于输出节点基本上没有延迟地移动共源共栅的栅极。 无源耦合消除了积极驱动共源共栅的栅极的需要。 在一些实施例中，级联栅极上所需的唯一电路可以是限制Vmax和2×Vmax之间的共源共栅栅极上的摆幅的偏置电路，其中Vmax是晶体管器件额定值。

公开(公告)号：US09182766B2

公开(公告)日：2015-11-10

申请号：US13793766

申请日：2013-03-11

Applicant: QUALCOMM Incorporated

Inventor： Joseph Duncan ,  Charles Derrick Tuten

IPC: H02M3/157 ,  G05F1/10 ,  H02M1/32 ,  H02M3/158 ,  H02M1/00

CPC classification number: G05F1/10 ,  H02M1/32 ,  H02M3/157 ,  H02M3/158 ,  H02M3/1588 ,  H02M2001/0025 ,  H02M2001/0035 ,  Y02B70/1466 ,  Y02B70/16

Abstract: Exemplary embodiments are related to a switching voltage regulator. A switching voltage regulator may include a current limit detector configured to detect an over-current condition. The switching voltage regulator may further include a pulse-width modulation (PWM) module coupled to the current limit detector and configured to convey a PWM signal based on a programmed switching frequency and an output voltage and in response to the over-current condition.

Abstract translation: 示例性实施例涉及开关电压调节器。 开关电压调节器可以包括被配置为检测过电流状况的电流限制检测器。 开关电压调节器还可以包括与电流限制检测器耦合的脉冲宽度调制（PWM）模块，其被配置为基于编程的开关频率和输出电压以及响应于过电流状态来传送PWM信号。