公开(公告)号：US09032358B2

公开(公告)日：2015-05-12

申请号：US13787647

申请日：2013-03-06

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Robert Won Chol Kim ,  Philip Michael Clovis ,  David Ian West

IPC: G06F17/50 ,  H01L27/02

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  G06F2217/40

Abstract: An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

Abstract translation: 集成电路包括核心逻辑和围绕核心逻辑的外围设置的多个接口块。 多个输入或输出（I / O）电路被分配给多个接口块中的一个。 I / O电路包括耦合到集成电路以外的器件的外部I / O电路和耦合到集成电路的内部I / O电路。 每个接口块包括设置在接口块的第一侧上的第一多个I / O电路和设置在接口块的第二侧上的第二多个I / O电路。 每个接口块还包括用于在第一多个I / O电路和第二多个I / O电路之间的接口块的接口逻辑，以及逻辑集线器，其包括驱动启动逻辑和捕获逻辑的最小长度的时钟分配 形成接口块的I / O电路。

公开(公告)号：US08957714B2

公开(公告)日：2015-02-17

申请号：US13831201

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Jan Christian Diffenderfer ,  Philip Michael Clovis ,  David Ian West

IPC: H03L7/00 ,  H03K5/159

CPC classification number: H03K5/159

Abstract: A master measure circuit is disclosed that may select from various nodes on a delay path carrying a signal. The master measure circuit measures the delay for propagation of the signal from one selected node to another selected node and controls an adjustable delay circuit in the delay path accordingly.

Abstract translation: 公开了可以在承载信号的延迟路径上的各个节点进行选择的主测量电路。 主测量电路测量信号从一个选定节点传播到另一个选定节点的延迟，并相应地控制延迟路径中的可调节延迟电路。

公开(公告)号：US20140253228A1

公开(公告)日：2014-09-11

申请号：US13787647

申请日：2013-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： Vaishnav Srinivas ,  Robert Won Chol Kim ,  Philip Michael Clovis ,  David Ian West

IPC: H01L27/02

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  G06F2217/40

Abstract: An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

Abstract translation: 集成电路包括核心逻辑和围绕核心逻辑的外围设置的多个接口块。 多个输入或输出（I / O）电路被分配给多个接口块中的一个。 I / O电路包括耦合到集成电路以外的器件的外部I / O电路和耦合到集成电路的内部I / O电路。 每个接口块包括设置在接口块的第一侧上的第一多个I / O电路和设置在接口块的第二侧上的第二多个I / O电路。 每个接口块还包括用于在第一多个I / O电路和第二多个I / O电路之间的接口块的接口逻辑，以及逻辑集线器，其包括驱动启动逻辑和捕获逻辑的最小长度的时钟分配 形成接口块的I / O电路。