公开(公告)号：US08225148B2

公开(公告)日：2012-07-17

申请号：US13112915

申请日：2011-05-20

申请人： Heng Tang ,  Gregory Burd ,  Zining Wu ,  Panu Chaichanavong

发明人： Heng Tang ,  Gregory Burd ,  Zining Wu ,  Panu Chaichanavong

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： G11B20/1423 ,  H03M5/145

摘要： The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information.

摘要翻译： 所公开的技术提供了基于游程长度限制代码和纠错码来编码数据以提供码字的系统和方法。 码字包括基于RLL码产生的RLL编码数据和基于纠错码产生的奇偶校验信息。 奇偶校验信息在RLL编码数据之间进行交织。 在一个实施例中，通过分别产生RLL编码数据和奇偶校验信息，以及在RLL编码数据之间交织奇偶校验信息来产生码字。 在一个实施例中，通过产生RLL编码数据并使用擦除解码来计算奇偶校验信息来产生码字。

公开(公告)号：US08036377B1

公开(公告)日：2011-10-11

申请号：US11955088

申请日：2007-12-12

申请人： Tze Lei Poo ,  Siu-Hung Fred Au ,  Gregory Burd ,  David Geddes ,  Heng Tang

发明人： Tze Lei Poo ,  Siu-Hung Fred Au ,  Gregory Burd ,  David Geddes ,  Heng Tang

IPC分类号： H04L9/00

CPC分类号： H04L9/28 ,  H04L9/0631 ,  H04L9/0637 ,  H04L2209/24

摘要： The disclosure provides a hardware architecture for encryption and decryption device. The hardware architecture can improve the encryption and decryption data rate by using parallel processing, and pipeline operation. Further, the hardware architecture can save footprint by sharing hardware components. Additionally, the hardware architecture can be associated with a memory to protect the information stored at the memory. The encryption device can include a tweaking value manager that is configured to generate an array of tweaking values corresponding to the array of data blocks based on a tweaking encryption key, a first encryption unit that is configured to encrypt a first portion of the array of data blocks into a first portion of encrypted data blocks based on corresponding tweaking values and a data encryption key, a second encryption unit that is configured to encrypt a second portion of the array of data blocks into a second portion of encrypted data blocks based on corresponding tweaking values and the data encryption key, and a data block combiner that is configured to combine the first portion of encrypted data blocks and the second portion of encrypted data blocks into an array of encrypted data blocks.

摘要翻译： 本公开提供了用于加密和解密设备的硬件架构。 硬件架构可以通过并行处理和流水线操作来提高加密和解密数据速率。 此外，硬件架构可以通过共享硬件组件来节省占用空间。 此外，硬件架构可以与存储器相关联，以保护存储在存储器中的信息。 加密装置可以包括调整值管理器，其被配置为基于调整加密密钥生成对应于数据块阵列的调整值阵列，第一加密单元，被配置为加密数据阵列的第一部分 基于对应的调整值将数据块嵌入加密数据块的第一部分和数据加密密钥中，第二加密单元被配置为基于相应的调整将数据块阵列的第二部分加密成加密数据块的第二部分 值和数据加密密钥，以及数据块组合器，其被配置为将加密数据块的第一部分和加密数据块的第二部分组合成加密数据块的阵列。

公开(公告)号：US07840878B1

公开(公告)日：2010-11-23

申请号：US11711286

申请日：2007-02-27

申请人： Heng Tang ,  Gregory Burd ,  Soichi Isono ,  Son Hong Ho ,  Vincent Wong ,  Zining Wu

发明人： Heng Tang ,  Gregory Burd ,  Soichi Isono ,  Son Hong Ho ,  Vincent Wong ,  Zining Wu

IPC分类号： G11C29/00 ,  H03M13/00

CPC分类号： G11B20/1803 ,  H03M13/09 ,  H03M13/253 ,  H03M13/2915

摘要： A system includes a host first-in first-out (FIFO) module, a first encoder module, a control module, a disk FIFO module, and a second encoder module. The host FIFO module receives a block having data and selectively receives a host logical block address (HLBA). The first encoder module generates a first checksum based on the data and the HLBA and generates a first encoded block. The control module appends the HLBA to the first encoded block and generates an appended block. The disk FIFO module receives the block from the host FIFO module. The second encoder module selectively generates a second checksum based on the HLBA and the data in the block received by the disk FIFO module. The second encoder module compares the block received by the disk FIFO module to the block received by the host FIFO module based on the first and second checksums.

摘要翻译： 系统包括主机先进先出（FIFO）模块，第一编码器模块，控制模块，盘FIFO模块和第二编码器模块。 主机FIFO模块接收具有数据的块并选择性地接收主机逻辑块地址（HLBA）。 第一编码器模块基于数据和HLBA生成第一校验和，并生成第一编码块。 控制模块将HLBA附加到第一编码块并生成附加块。 磁盘FIFO模块从主机FIFO模块接收该块。 第二编码器模块基于HLBA和由盘FIFO模块接收的块中的数据选择性地产生第二校验和。 第二编码器模块基于第一和第二校验和将由盘FIFO模块接收的块与由主机FIFO模块接收的块进行比较。

公开(公告)号：US07774675B1

公开(公告)日：2010-08-10

申请号：US11481141

申请日：2006-07-05

申请人： Adina Matache ,  Heng Tang ,  Gregory Burd ,  Aditya Ramamoorthy ,  Jun Xu ,  Zining Wu

发明人： Adina Matache ,  Heng Tang ,  Gregory Burd ,  Aditya Ramamoorthy ,  Jun Xu ,  Zining Wu

IPC分类号： H03M13/00

CPC分类号： H03M13/1177 ,  H03M13/116 ,  H03M13/1188

摘要： A MIMO transmitter comprises a scrambler; an encoder parser responsive to the scrambler; a forward error correction encoder responsive to the encoder parser, wherein the encoder applies a parity check matrix derived from a base matrix; an interleaver responsive to the forward error correction encoder; a QAM mapping module responsive to the interleaver; an inverse fast Fourier transform module responsive to the QAM mapping module; and an output module responsive to the inverse fast Fourier transform module.

摘要翻译： MIMO发射机包括扰频器; 响应于扰频器的编码器解析器; 响应于所述编码器解析器的前向纠错编码器，其中所述编码器应用从基本矩阵导出的奇偶校验矩阵; 响应于前向纠错编码器的交织器; 响应于交织器的QAM映射模块; 响应于QAM映射模块的快速傅立叶逆变换模块; 以及响应快速傅立叶逆变换模块的输出模块。

公开(公告)号：US08166370B1

公开(公告)日：2012-04-24

申请号：US11805344

申请日：2007-05-23

申请人： Heng Tang ,  Zining Wu ,  Gregory Burd ,  Pantas Sutardja

发明人： Heng Tang ,  Zining Wu ,  Gregory Burd ,  Pantas Sutardja

IPC分类号： G11C29/00

CPC分类号： G06F11/1076 ,  G06F11/08 ,  G06F11/1443 ,  G11C29/00 ,  H03M13/09 ,  H03M13/1515 ,  H03M13/155 ,  H03M13/611 ,  H03M13/618

摘要： A Redundant Array of Inexpensive Disks (RAID) controller comprises a RAID error correction code (ECC) encoder module that receives data for storage and that generates code words for data drives and one or more parity drives, which have physical locations. The code words are generated based on the data and a cyclic code generator polynomial. Logical locations correspond to index positions in the cyclic code generator polynomial. A mapping module maps the physical locations of the data and parity drives to the logical locations. The mapping module adds a new data drive to an unused one of the logical locations. A difference generating module generates a difference code word based on the new data drive. The RAID ECC encoder module encodes the difference code word and adds the encoded difference code word to an original code word generated before the new data drive is added.

摘要翻译： 一个廉价磁盘冗余阵列（RAID）控制器包括一个RAID纠错码（ECC）编码器模块，它接收用于存储的数据，并产生数据驱动器的代码字和一个或多个具有物理位置的奇偶校验驱动器。 基于数据和循环码生成多项式生成码字。 逻辑位置对应于循环码生成多项式中的索引位置。 映射模块将数据和奇偶校验驱动器的物理位置映射到逻辑位置。 映射模块将新的数据驱动器添加到未使用的逻辑位置。 差异生成模块基于新的数据驱动器生成差分码字。 RAID ECC编码器模块对差分码字进行编码，并将经编码的差分码字添加到添加新数据驱动器之前生成的原始码字。

公开(公告)号：US08155308B1

公开(公告)日：2012-04-10

申请号：US11973856

申请日：2007-10-10

申请人： Tze Lei Poo ,  Heng Tang ,  Siu-Hung Fred Au ,  Gregory Burd

发明人： Tze Lei Poo ,  Heng Tang ,  Siu-Hung Fred Au ,  Gregory Burd

IPC分类号： H04L9/06

CPC分类号： H04L9/0631 ,  H04L9/0637 ,  H04L9/0693 ,  H04L2209/125

摘要： A cryptographic device comprises a first pipeline stage, a pipeline register, and a second pipeline stage. The first pipeline stage comprises a first byte substitution module that performs mathematical operations on a received byte and outputs an intermediate value based on the mathematical operations. The pipeline register stores the intermediate value. The second pipeline stage comprises a second byte substitution module and a column mixing module. The second byte substitution module generates a replacement byte corresponding to the received byte based on mathematical operations performed on the stored intermediate value. The column mixing module transforms groups of four bytes of a plurality of replacement bytes including the replacement byte.

摘要翻译： 加密装置包括第一流水线级，流水线寄存器和第二流水线级。 第一流水线级包括对接收到的字节执行数学运算的第一字节替换模块，并且基于数学运算输出中间值。 流水线寄存器存储中间值。 第二流水线级包括第二字节替代模块和列混合模块。 第二字节替换模块基于对所存储的中间值执行的数学运算，生成与接收字节对应的替换字节。 列混合模块转换包括替换字节的多个替换字节的四个字节的组。

公开(公告)号：US07782232B2

公开(公告)日：2010-08-24

申请号：US12187160

申请日：2008-08-06

申请人： Xueshi Yang ,  Gregory Burd ,  Heng Tang ,  Panu Chaichanavong ,  Zining Wu

发明人： Xueshi Yang ,  Gregory Burd ,  Heng Tang ,  Panu Chaichanavong ,  Zining Wu

IPC分类号： H03M13/00

CPC分类号： H03M13/2945 ,  G06F11/1068 ,  H03M13/033 ,  H03M13/1515 ,  H03M13/2903 ,  H03M13/2906

摘要： Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level.

摘要翻译： 描述使用广义级联码（GCC）的编码和解码的系统，装置和方法。 方法包括接收数据; 对所接收的数据进行编码以获得第一编码数据; 对第一编码数据进行编码，直到GCC编码达到中间级; 并终止中级的GCC编码。

公开(公告)号：US20090040081A1

公开(公告)日：2009-02-12

申请号：US12187160

申请日：2008-08-06

申请人： Xueshi Yang ,  Gregory Burd ,  Heng Tang ,  Panu Chaichanavong ,  Zinging Wu

发明人： Xueshi Yang ,  Gregory Burd ,  Heng Tang ,  Panu Chaichanavong ,  Zinging Wu

IPC分类号： H03M13/00

CPC分类号： H03M13/2945 ,  G06F11/1068 ,  H03M13/033 ,  H03M13/1515 ,  H03M13/2903 ,  H03M13/2906

摘要： Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level.

摘要翻译： 描述使用广义级联码（GCC）的编码和解码的系统，装置和方法。 方法包括接收数据; 对所接收的数据进行编码以获得第一编码数据; 对第一编码数据进行编码，直到GCC编码达到中间级; 并终止中级的GCC编码。

公开(公告)号：US08694850B1

公开(公告)日：2014-04-08

申请号：US13486917

申请日：2012-06-01

申请人： Heng Tang

发明人： Heng Tang

IPC分类号： H03M13/00

CPC分类号： H03M13/2909 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/293 ,  H03M13/2948

摘要： A method, computer-readable medium storing instructions, and apparatus for decoding column codewords of a two-dimensional product code having intersecting row and column codewords is presented that reduces the number of computations needed to decode a column codeword. The method includes computing an error location polynomial for all column codewords based on known failure locations in intersecting row codewords, computing a syndrome polynomial for each column codeword, and correcting errors in the column codeword according to error evaluation values generated based on the syndrome polynomial and the stored error location polynomial.

摘要翻译： 提出一种存储指令的方法，计算机可读介质和用于解码具有相交的行和列码字的二维乘积码的列码字的装置，其减少了解码列码字所需的计算次数。 该方法包括：基于相交行码字中的已知故障位置计算所有列码字的错误位置多项式，根据每个列码字计算校正子多项式，以及根据基于多项式生成的错误评估值校正列码字中的错误，以及 存储的错误位置多项式。

公开(公告)号：US08032812B1

公开(公告)日：2011-10-04

申请号：US11867356

申请日：2007-10-04

申请人： Xueshi Yang ,  Zining Wu ,  Heng Tang

发明人： Xueshi Yang ,  Zining Wu ,  Heng Tang

IPC分类号： H03M13/00

CPC分类号： H04L1/0052 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/2909 ,  H03M13/293 ,  H04L1/0065

摘要： A method and system for error correction decoding uses concatenated error correction decoders. A channel decoder receives encoded user data from a transmission channel, decodes the bits of the user data, and generates erasure information for the decoded bits. The decoded bits and erasure information is received by an outer ECC decoder, which first performs erasure decoding. If the erasure decoding is successful, then the decoded user data is output. If the erasure decoding is not successful, then the outer ECC decoder performs the more complex error decoding. Thus, error decoding need not be performed for user data that can be successfully decoded using erasure decoding. The extra operations required to perform error decoding is avoided. In this manner, the complexity of the overall decoding process is reduced, significantly reducing the computation power required, while maintaining the desired performance level.

摘要翻译： 用于纠错解码的方法和系统使用连接的纠错解码器。 信道解码器从传输信道接收编码用户数据，对用户数据的比特进行解码，并生成解码比特的擦除信息。 解码的比特和擦除信息由外部ECC解码器接收，该外部ECC解码器首先执行擦除解码。 如果擦除解码成功，则输出解码的用户数据。 如果擦除解码不成功，则外部ECC解码器执行更复杂的错误解码。 因此，不需要对可以使用擦除解码成功解码的用户数据执行错误解码。 避免执行错误解码所需的额外操作。 以这种方式，减少整体解码过程的复杂性，显着降低所需的计算能力，同时保持所需的性能水平。