公开(公告)号：US20200252072A1

公开(公告)日：2020-08-06

申请号：US16373653

申请日：2019-04-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu

IPC: H03L7/199 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/091 ,  G11C7/22

Abstract: A clock and data recovery circuit which includes a phase detector, a digital loop filter and a phase interpolator is provided according to an exemplary embodiment of the disclosure. The phase detector is configured to detect a phase difference between a data signal and a clock signal. The phase interpolator is configured to generate the clock signal according to an output of the digital loop filter. The digital loop filter is configured to operate automatically according a default value stored in the digital loop filter under an initial status, so as to establish a default phase shift or a default frequency difference of the clock signal with respect to the data signal before the data signal and the clock signal are compared.

公开(公告)号：US10326622B2

公开(公告)日：2019-06-18

申请号：US15836903

申请日：2017-12-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Sheng-Wen Chen ,  Shin-Yang Sun ,  Wei-Yung Chen ,  Jen-Chu Wu ,  Chih-Ming Chen

IPC: H04L25/03 ,  H04L25/497 ,  H04L7/00 ,  G06F3/06

Abstract: An equalizer tuning method for a memory storage device is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal; modulating the first signal by a first modulation circuit according to a first type parameter and modulating the first signal by a second modulation circuit according to a second type parameter; detecting a signal eye-width value and a signal eye-height value of the modulated first signal; and adjusting the first type parameter according to the detected signal eye-width value and adjusting the second type parameter according to the detected signal eye-height value.

公开(公告)号：US20150311907A1

公开(公告)日：2015-10-29

申请号：US14309879

申请日：2014-06-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu ,  An-Chung Chen

IPC: H03L7/091 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1093 ,  H03L7/0805 ,  H03L7/0812

Abstract: A sampling circuit module, a memory control circuit unit, and a method for sampling data are provided. The sampling circuit module includes a state machine circuit, a first delay line circuit, a second delay line circuit and a delay signal output circuit. In response to a first control signal, the state machine circuit outputs a second control signal and/or a third control signal. The first delay line circuit is configured to receive a reference clock signal and the second control signal to output a first delay clock signal. The second delay line circuit is configured to receive the reference clock signal and the third control signal to output a second delay clock signal. The delay signal output circuit is configured to receive the first delay clock signal and the second delay clock signal to output a third delay clock signal.

Abstract translation: 提供采样电路模块，存储器控制电路单元和数据采样方法。 采样电路模块包括状态机电路，第一延迟线电路，第二延迟线电路和延迟信号输出电路。 响应于第一控制信号，状态机电路输出第二控制信号和/或第三控制信号。 第一延迟线电路被配置为接收参考时钟信号和第二控制信号以输出第一延迟时钟信号。 第二延迟线电路被配置为接收参考时钟信号和第三控制信号以输出第二延迟时钟信号。 延迟信号输出电路被配置为接收第一延迟时钟信号和第二延迟时钟信号以输出第三延迟时钟信号。

公开(公告)号：US20140219382A1

公开(公告)日：2014-08-07

申请号：US13853056

申请日：2013-03-29

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu

IPC: H04L25/02

CPC classification number: H04L25/0266

Abstract: A signal transmission circuit of an electronic device is provided. The electronic device is coupled to a signal reception circuit of a host via the signal transmission circuit. The signal transmission circuit includes a driving circuit module and a signal detection module. The driving circuit module provides at least one initialized signal and a detection signal. The initialized signal is output prior to the detection signal. The signal detection module is coupled to the signal reception circuit via a signal detection terminal. The initialized signal reduces a signal reference level of a reception terminal of the signal reception circuit. The signal detection module determines the type of the transmission interface of the signal reception circuit according to whether the detection signal of the signal detection terminal satisfies a predetermined threshold value. Furthermore, a method for detecting the signal transmission interface is provided.

Abstract translation: 提供电子设备的信号传输电路。 电子设备经由信号传输电路耦合到主机的信号接收电路。 信号传输电路包括驱动电路模块和信号检测模块。 驱动电路模块提供至少一个初始化信号和检测信号。 初始化信号在检测信号之前被输出。 信号检测模块通过信号检测端子耦合到信号接收电路。 初始化信号降低信号接收电路的接收端的信号参考电平。 信号检测模块根据信号检测端子的检测信号是否满足预定的阈值来确定信号接收电路的传输接口的类型。 此外，提供了一种用于检测信号传输接口的方法。