公开(公告)号：US20200073453A1

公开(公告)日：2020-03-05

申请号：US16118749

申请日：2018-08-31

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Kristof Blutman ,  Juan Diego Echeverri Escobar ,  Jose de Jesus Pineda de Gyvez ,  Jurgen Geerlings ,  Hamed Fatemi

IPC: G06F1/26 ,  H02M3/137 ,  H02M3/07

Abstract: An electronic device including a power source providing a source voltage, a capacitor, a primary regulator circuit, an always-on load that is active during a low power mode, and a recycle control circuit. The primary regulator circuit receives the source voltage and has an output that maintains a charge on the capacitor during an active mode. The primary regulator circuit does not contribute to a charge on the capacitor during the low power mode. The recycle control circuit includes a select circuit and a select control circuit. The select circuit selects, based on a control signal, between the voltage of the capacitor and at least one supply voltage including or otherwise developed using the source voltage to provide power to the always-on load during the low power mode. The select control circuit provides the control signal to control power provided to the always-on load during the low power mode.

公开(公告)号：US09634649B2

公开(公告)日：2017-04-25

申请号：US14792276

申请日：2015-07-06

Applicant: NXP B.V.

Inventor： Juan Echeverri Escobar ,  Jose de Jesus Pineda de Gyvez ,  Sebastien Antonius Josephus Fabrie

IPC: H03K3/289 ,  H03K3/356 ,  H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/012 ,  H03K3/037 ,  H03K19/0016

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.

公开(公告)号：US20150346742A1

公开(公告)日：2015-12-03

申请号：US14293785

申请日：2014-06-02

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Ralf Malzahn ,  Vibhu Sharma ,  Jose de Jesus Pineda de Gyvez ,  Peter Thueringer

IPC: G05F1/46

CPC classification number: G05F1/46 ,  G06F1/32

Abstract: A system including: a voltage converter configured to convert a voltage from a power source to a different voltage; a memory coupled to the voltage converter; a digital logic circuit; and a level shifter coupled between the memory and digital logic circuit; wherein leakage current from the memory is stored in a capacitance in the digital logic circuit, wherein the voltage converter is further coupled to a node between the memory and digital logic circuit, and wherein the voltage converter is configured to: monitor a voltage at the node wherein the node has a desired operating voltage value; and adjust the voltage at the node when the voltage at the node varies from the desired operating voltage value.

Abstract translation: 一种系统，包括：电压转换器，被配置为将来自电源的电压转换成不同的电压; 耦合到电压转换器的存储器; 数字逻辑电路; 以及耦合在存储器和数字逻辑电路之间的电平移位器; 其中来自所述存储器的泄漏电流被存储在所述数字逻辑电路中的电容中，其中所述电压转换器进一步耦合到所述存储器和数字逻辑电路之间的节点，并且其中所述电压转换器被配置为：监视所述节点处的电压 其中所述节点具有期望的工作电压值; 并且当节点电压从期望的工作电压值变化时调节节点处的电压。