Abstract:
A CMOS image sensor having two ASPs can reduce increasing design difficulty as arising from a pixel array becoming larger and larger. The image sensor includes a selection circuit for transmitting outputs of CDS circuits through four divided buses to reduce parasitic loading and achieve high-speed operation. Then, the selecting circuit transmits red and blue pixels to a first ASP, and transmits green pixels to a second ASP, so as to relax the specification requirements of the ASP.
Abstract:
A method for resetting image sensing and an image sensing device using the same are provided. The method for resetting image sensing includes generating a plurality of reset signals and a plurality of control signals, and using the reset signals and the control signals to control a pixel array to reset and expose. The pixel array has a plurality of pixel blocks, each of the pixel blocks has a plurality of pixel sensing units. When the plurality of pixel sensing units of one of the pixel blocks expose to acquire a plurality of sensing signals sequentially, the plurality of pixel sensing units of another one of the pixel blocks are reset.
Abstract:
An image sensor capable of repairing column readout circuits includes a pixel array, a column readout circuit array, an addressing unit and a repairing unit. The column readout circuit array includes a plurality of column readout circuit group and a redundant column readout circuit group, which is placed on a side of the plurality of column readout circuit groups and consists of a specific number of redundant column readout circuits. The repairing unit is utilized for shifting in order pixel column groups, which are originally coupled to column readout circuit groups starting from a first column readout circuit group having defects, to couple to the column readout circuit groups next to the first column readout circuit group and the redundant column readout circuit group.
Abstract:
An automatic clock generation system is used for automatically outputting a sampling signal and a holding signal to an analog front end circuit and for sampling the analog signal. The clock generation system comprises a clock generator generating a plurality of clock signals and a comparing module. According to the plurality of clock signals, the comparing module compares the analog signal with a first reference signal and outputs a first comparison signal. The comparing module further compares the digital signal outputted by the analog front end circuit with a second reference signal and outputs a second comparison signal. The clock generator selectively outputs a first clock signal, corresponding to the first comparison signal, of the plurality of clock signals as the sampling signal when the first comparison signal received by the clock generator is at a high state. The clock generator further selectively outputs a second clock signal, corresponding to the second comparison signal, of the plurality of clock signals as the holding signal when the second comparison signal received by the clock generator is at the high state.
Abstract:
A digital-to-analog converter (DAC) is disclosed, which provides different bias voltages to the most significant bits (MSBs) and the least significant bits (LSBs) of the digital signal. These two bias voltages can be adjusted according to the match among the current source cells, and maintain a particular proportional relationship. The DAC further includes a bias converter for receiving the first bias voltage, and adjusting the second bias voltage according to the match among the current source cells.
Abstract:
The invention provides a transient voltage detecting circuit for detecting changes of voltage in an electronic system which has a first power supply (VDD), a second power supply (VDD), a third power supply (VDD), a fourth power supply (VDD), a first ground (GND), and a second ground (GND). The voltage of the first VDD is substantially equal to that of the second VDD. The voltage of the third VDD is substantially equal to that of the fourth VDD. The voltage of the first GND is substantially equal to that of the second GND. The circuit according to the invention can detect a positive or negative transient voltage once that occurs at the first VDD, the second VDD, the third VDD, or the fourth VDD.
Abstract:
A semiconductor substrate has a V-shape structure positioned in the semiconductor substrate. A first ion implantation process is then performed to form a first doping region around the V-shape structure in the semiconductor substrate. Following this, a first dielectric layer is formed on surfaces of the semiconductor substrate and the first doping region. A floating gate is formed on the first dielectric layer over the first doping region and a second dielectric layer is formed on the floating gate, respectively. A controlling gate is then formed on the second dielectric layer. Finally, a second ion implantation process is performed utilizing the controlling gate as a mask to form a second doping region in the semiconductor substrate.
Abstract:
Embodiments of the present invention provide a correlated double sampling (CDS) circuit and a CMOS image sensor unit using the CDS circuit. The CDS circuit shifts levels of sampled sensing signal and reset signal with equal amounts. Thus a voltage difference of the sampled sensing signal and the reset signal remains unchanged, and their levels may fall within a linear input range by adjusting their levels. Compared to a conventional CDS circuit, a gain of the CDS circuit provided by the embodiment of the present invention is not reduced, and thus a design complexity of a rear circuit thereof is lower, and an induced noise is relatively low. Furthermore, the CMOS image sensor unit using the CDS circuit provided by the embodiment also has these advantages.
Abstract:
A method for resetting image sensing and an image sensing device using the same are provided. The method for resetting image sensing includes generating a plurality of reset signals and a plurality of control signals, and using the reset signals and the control signals to control a pixel array to reset and expose. The pixel array has a plurality of pixel blocks, each of the pixel blocks has a plurality of pixel sensing units. When the plurality of pixel sensing units of one of the pixel blocks expose to acquire a plurality of sensing signals sequentially, the plurality of pixel sensing units of another one of the pixel blocks are reset.
Abstract:
A variable-gain amplifier circuit and a method of changing gain amplifier paths are provided for receiving and amplifying an image sensing signal. The variable-gain amplifier circuit includes variable path and gain amplifier circuits. According to the amplification factor for the image sensing signal, the gain amplifier paths in the variable path and gain amplifier circuits are changed based on a control signal, so as to achieve the appropriate construction of the variable-gain amplifier circuit. The image sensing signal generates the required image result through appropriate numbers of variable gain amplifiers, thereby decreasing the power consumption of the circuit and reducing the design requirement of the circuit.