公开(公告)号：US20190004802A1

公开(公告)日：2019-01-03

申请号：US15637562

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Stephen J. Tarsa ,  Gokce Keskin ,  Gautham N. Chinya ,  Hong Wang

IPC: G06F9/38 ,  G06N3/04

Abstract: A processor, including: an execution unit including branching circuitry; a branch predictor, including a hard-to-predict (HTP) branch filter to identify an HTP branch; and a special branch predictor to receive identification of an HTP branch from the HTP branch filter, the special branch predictor including a convolutional neural network (CNN) branch predictor to predict a branching action for the HTP branch.

公开(公告)号：US20170091655A1

公开(公告)日：2017-03-30

申请号：US14865124

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Tsung-Han Lin ,  Gokce Keskin ,  Hsiang-Tsung Kung ,  She-Hwa Yen ,  Hong Wang

IPC: G06N99/00

CPC classification number: G06N20/00 ,  G06F9/3836 ,  G06F15/76

Abstract: A processor includes a front end to decode an instruction, an allocator to pass the instruction to a nearest neighbor logic unit (NNLU) to execute the instruction, and a retirement unit to retire the instruction. The NNLU includes logic to determine input of the instruction for which nearest neighbors will be calculated, transform the input, retrieve candidate atoms for which the nearest neighbors will be calculated, compute distance between the candidate atoms and the input, and determine the nearest neighbors for the input based upon the computed distance.

公开(公告)号：US09374250B1

公开(公告)日：2016-06-21

申请号：US14573343

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Tawfiq Musah ,  Gokce Keskin ,  Ganesh Balamurugan ,  James E. Jaussi ,  Bryan K. Casper

IPC: H03H7/30 ,  H04L25/03 ,  H04L7/02

CPC classification number: H04L25/03057 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/03146 ,  H04L25/14

Abstract: Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.

Abstract translation: 一些实施例包括具有用于接收输入信号的输入的装置和方法，用于接收具有不同相位以对输入信号进行采样的时钟信号的附加输入以及具有DFE切片的判决反馈均衡器（DFE）。 DFE片包括多个数据比较器，用于基于输入信号的采样来提供数据信息，以及多个相位误差比较器，以提供与输入信号的采样相关联的相位误差信息。 DFE切片的相位误差比较器的数量不大于DFE切片的数据比较器的数量。