公开(公告)号：US20220129399A1

公开(公告)日：2022-04-28

申请号：US17431739

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Kun Tian ,  Yan Zhao ,  Yu Zhang

IPC: G06F13/28

Abstract: Systems, apparatuses and methods may provide for a frontend driver that notifies a hypervisor of a map request from a guest driver of a device, wherein the device is passed through to and directly controlled by a virtual machine, and wherein the map request is associated with an attempt of the device to access a guest memory page in a virtualized execution environment. The frontend driver may also determine whether the guest memory page is pinned and send a map hypercall to the hypervisor if the guest memory page is not pinned. Additionally, the hypervisor may determine that the guest memory page is pinned, determine, based on a direct memory access (DMA) bitmap, that an unmap request from the guest driver has been issued, and unpin the guest memory page.

公开(公告)号：US10854539B2

公开(公告)日：2020-12-01

申请号：US16509387

申请日：2019-07-11

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC: H01L23/498 ,  H01L21/48

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US10778600B2

公开(公告)日：2020-09-15

申请号：US16073683

申请日：2016-03-30

Applicant: INTEL CORPORATION

Inventor： Huifeng Le ,  Wenjian Shao ,  Yu Zhang ,  Shao-Wen Yang ,  Heng Juen Han ,  Xiaowen Zhang

IPC: H04L12/911 ,  H04N7/18 ,  H04L29/08 ,  H04L12/26

Abstract: Techniques are provided for adaptive distribution of video analysis workload over a network of video processor nodes. The nodes may include, for example, internet protocol (IP) cameras, video recorders and/or data centers. The network may also include a management system configured to assign video analysis tasks to the nodes based on the node resources and predictive modelling of the node workload. The management system may re-distribute the tasks based on performance monitoring. Some assigned tasks may be bound to the node while other tasks may be transferrable, by the node, to other nodes. The nodes may be configured to determine which of the transferrable tasks will be locally executed or transferred based on a check of resource usage against a usage policy that specifies thresholds for the determinations. The nodes may be configured to transmit video analysis packets, including image data, analysis completion status and analysis results, to other nodes.

公开(公告)号：US20170187419A1

公开(公告)日：2017-06-29

申请号：US14998254

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Zhang ,  Mathew J. Manusharow ,  Adel A. Elsherbini ,  Henning Braunisch ,  Kemal Aygun

IPC: H04B3/32 ,  H04L5/14

CPC classification number: H04B3/32 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: Embodiments are generally directed to a shielded bundle interconnect. An embodiment of an apparatus includes multiple signal bundles, the signal bundles including a first signal bundle including a first plurality of signals and a second signal bundle including a second plurality of signals; and a lithographic via shielding to provide electromagnetic shielding, the lithographic via shielding located at least in part between the first signal bundle and the second signal bundle, wherein the lithographic via shielding includes at least a via generated by a lithographic via process. The lithographic via shielding partially or completely surrounds at least one of the signal bundles of the apparatus.

公开(公告)号：US09230900B1

公开(公告)日：2016-01-05

申请号：US14575956

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC: H01L23/52 ,  H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.