公开(公告)号：US6160431A

公开(公告)日：2000-12-12

申请号：US547576

申请日：2000-04-12

申请人： Patrick J. Crotty

发明人： Patrick J. Crotty

IPC分类号： H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223

摘要： A power-on reset circuit is provided which uses a dual voltage detection circuit to output a voltage detection signal. The dual voltage detection circuit is coupled to a first supply voltage terminal, a second supply voltage terminal, and a ground terminal. The voltage detection signal indicates whether the first supply voltage provided on the first supply voltage terminal is greater than an adequate voltage level. Furthermore, the voltage detection signal is driven by circuits powered by a second supply voltage provided on the second supply voltage terminal. One embodiment of the dual-voltage detection circuit comprises a first transistor coupled in series with a second transistor between the first supply voltage terminal and the ground terminal, as well as a third transistor coupled in series with a fourth transistor between the second supply voltage terminal and the ground terminal. Furthermore, some embodiments of the present invention also include a low pass filter coupled to the dual-voltage detection circuit to prevent spurious noise and ground bounces from causing a reset.

公开(公告)号：US08667192B2

公开(公告)日：2014-03-04

申请号：US13037234

申请日：2011-02-28

申请人： William E. Allaire ,  Bradley L. Taylor ,  Ting Lu ,  Sandeep Dutta ,  Patrick J. Crotty ,  Hassan K. Bazargan ,  Hy V. Nguyen ,  Shashank Bhonge

发明人： William E. Allaire ,  Bradley L. Taylor ,  Ting Lu ,  Sandeep Dutta ,  Patrick J. Crotty ,  Hassan K. Bazargan ,  Hy V. Nguyen ,  Shashank Bhonge

IPC分类号： G06F13/00 ,  G06F12/00 ,  G06F13/24 ,  G06F1/00 ,  H03K19/173

CPC分类号： G06F13/10 ,  G06F1/26 ,  G06F1/3287 ,  G06F15/7867 ,  G06F15/7871 ,  Y02D10/171

摘要： An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

摘要翻译： 集成电路可以包括被配置为执行程序代码的处理器系统。 处理器系统可以是硬连线的并且包括处理器硬件资源。 IC还可以包括可配置为实现不同物理电路的可编程电路。 可编程电路可以耦合到处理器系统。 可编程电路可以被配置为共享处理器系统的处理器硬件资源的使用。 处理器系统还可以控制诸如上电和/或关断的可编程电路的方面，并且还可以配置可编程电路以在其中实现一个或多个不同的物理电路。

公开(公告)号：US08040153B1

公开(公告)日：2011-10-18

申请号：US12694169

申请日：2010-01-26

申请人： John G. O'Dwyer ,  Patrick J. Crotty

发明人： John G. O'Dwyer ,  Patrick J. Crotty

IPC分类号： H03K19/177

CPC分类号： H03M9/00

摘要： In one embodiment, a method and apparatus for configuring the internal memory cells of an integrated circuit through the logic fabric are disclosed. For example, an integrated circuit according to one embodiment includes a logic fabric and a plurality of input/output blocks coupled to the logic fabric, wherein the plurality of input/output blocks is positioned around the periphery of the logic fabric. The plurality of input/output blocks therefore forms a ring around the logic fabric, wherein a data path and a clock path are formed along the periphery of the logic fabric through the plurality of input/output blocks.

摘要翻译： 在一个实施例中，公开了一种用于通过逻辑结构配置集成电路的内部存储单元的方法和装置。 例如，根据一个实施例的集成电路包括逻辑结构和耦合到逻辑结构的多个输入/输出块，其中多个输入/输出块位于逻辑结构的外围周围。 因此，多个输入/输出块在逻辑结构周围形成环，其中通过多个输入/输出块沿着逻辑结构的外围形成数据路径和时钟路径。

公开(公告)号：US20110147949A1

公开(公告)日：2011-06-23

申请号：US13038746

申请日：2011-03-02

申请人： James Karp ,  Steven P. Young ,  Bernard J. New ,  Scott S. Nance ,  Patrick J. Crotty

发明人： James Karp ,  Steven P. Young ,  Bernard J. New ,  Scott S. Nance ,  Patrick J. Crotty

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H03K19/177 ,  G06F17/5068 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19041 ,  H01L2924/37001 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die.

摘要翻译： 描述形成混合集成电路器件的方法的实施例。 该方法的该实施例包括：使用第一光刻形成第一裸片，其中第一裸片位于衬底上; 以及使用第二光刻形成第二管芯，其中所述第二管芯位于所述第一管芯上。 用于形成第一裸片的第一光刻是比用于形成第二裸片的第二光刻更大的光刻。 第一个模具是IO模具。

公开(公告)号：US07919845B2

公开(公告)日：2011-04-05

申请号：US12004906

申请日：2007-12-20

申请人： James Karp ,  Steven P. Young ,  Bernard J. New ,  Scott S. Nance ,  Patrick J. Crotty

发明人： James Karp ,  Steven P. Young ,  Bernard J. New ,  Scott S. Nance ,  Patrick J. Crotty

IPC分类号： H01L23/02

CPC分类号： H03K19/177 ,  G06F17/5068 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19041 ,  H01L2924/37001 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Formation of a hybrid integrated circuit device is described. A design for the integrated circuit is obtained and separated into at least two portions responsive to component sizes. A first die is formed for a first portion of the hybrid integrated circuit device using at least in part a first minimum dimension lithography. A second die is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die has the second minimum dimension lithography as a smallest lithography used for the forming of the second die. The first die and the second die are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device.

摘要翻译： 描述了混合集成电路器件的形成。 获得集成电路的设计并将其分离成响应于部件尺寸的至少两个部分。 使用至少部分第一最小尺寸光刻形成用于混合集成电路器件的第一部分的第一裸片。 使用至少部分第二最小尺寸光刻形成用于装置的第二部分的第二模具，其中第二模具具有作为用于形成第二模具的最小光刻的第二最小尺寸光刻。 第一管芯和第二管芯分别通过其耦合互连件彼此附接以提供混合集成电路器件。

公开(公告)号：US20090160482A1

公开(公告)日：2009-06-25

申请号：US12004906

申请日：2007-12-20

申请人： James Karp ,  Steven P. Young ,  Bernard J. New ,  Scott S. Nance ,  Patrick J. Crotty

发明人： James Karp ,  Steven P. Young ,  Bernard J. New ,  Scott S. Nance ,  Patrick J. Crotty

IPC分类号： H03K19/177 ,  G06F17/50 ,  H01L23/48 ,  H01L21/58

CPC分类号： H03K19/177 ,  G06F17/5068 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19041 ,  H01L2924/37001 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Formation of a hybrid integrated circuit device (400) is described. A design for the integrated circuit (100) is obtained and separated into at least two portions responsive to component sizes. A first die (200) is formed for a first portion of the hybrid integrated circuit device (400) using at least in part a first minimum dimension lithography. A second die (300) is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die (300) has the second minimum dimension lithography as a smallest lithography used for the forming of the second die (300). The first die (200) and the second die (300) are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device (400).

摘要翻译： 描述了混合集成电路器件（400）的形成。 获得集成电路（100）的设计，并将其分离成响应于部件尺寸的至少两个部分。 使用至少部分第一最小尺寸光刻法，为混合集成电路器件（400）的第一部分形成第一裸片（200）。 使用至少部分第二最小尺寸光刻形成用于装置的第二部分的第二裸片（300），其中第二裸片（300）具有作为用于形成第二裸片的最小光刻的第二最小尺寸光刻 死（300）。 第一管芯（200）和第二管芯（300）分别通过其连接互连件彼此附接以提供混合集成电路器件（400）。