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    Reducing shunts in memories with phase-change material
    21.
    发明申请
    Reducing shunts in memories with phase-change material 有权
    用相变材料减少记忆中的分流

    公开(公告)号：US20050136557A1

    公开(公告)日：2005-06-23

    申请号：US11038336

    申请日：2005-01-19

    Applicant: Daniel Xu ,  Chien Chiang

    Inventor： Daniel Xu ,  Chien Chiang

    IPC: H01L45/00 ,  H01L21/00

    CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683

    Abstract: A memory cell may include a phase-change material. Adhesion between the phase-change material and a dielectric or other substrate may be enhanced by using an adhesion enhancing interfacial layer. Conduction past the phase-change material through the interfacial layer may be reduced by providing a discontinuity or other feature that reduces or prevents conduction along said interfacial layer.

    Abstract translation: 存储单元可以包括相变材料。 可以通过使用粘合增强界面层来增强相变材料与电介质或其它基底之间的粘附。 可以通过提供减少或阻止沿着所述界面层传导的不连续性或其它特征来减少穿过相变材料通过界面层的传导。

    Barrier material encapsulation of programmable material
    23.
    发明授权
    Barrier material encapsulation of programmable material 有权
    阻挡材料封装可编程材料

    公开(公告)号：US06642102B2

    公开(公告)日：2003-11-04

    申请号：US09896530

    申请日：2001-06-30

    Applicant: Daniel Xu

    Inventor： Daniel Xu

    IPC: H01L21336

    CPC classification number: H01L21/76897 ,  H01L23/525 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  Y10S438/90 ,  H01L2924/00

    Abstract: A method comprising forming as stacked materials on a substrate, a volume of programmable material and a signal line, conformably forming a first dielectric material on the stacked materials, forming a second dielectric material on the first material, etching an opening in the second dielectric material with an etchant that, between the first dielectric material and the second dielectric material, favors removal of the second dielectric material, and forming a contact in the opening to the stacked materials. An apparatus comprising a contact point formed on a substrate, a volume of programmable material formed on the contact point, a signal line formed on the volume of programmable material, a first dielectric material conformally formed on the signal line, a different second dielectric material formed on the first dielectric material, and a contact formed through the first dielectric material and the second dielectric material to the signal line.

    Abstract translation: 一种方法，包括在衬底上形成堆叠的材料，一定量的可编程材料和信号线，在所述堆叠材料上顺应地形成第一电介质材料，在所述第一材料上形成第二电介质材料，蚀刻所述第二电介质材料 在第一电介质材料和第二电介质材料之间，蚀刻剂有利于去除第二电介质材料，并且在开口中形成与层叠材料的接触。 一种设备，包括形成在基板上的接触点，形成在接触点上的可编程材料的体积，形成在可编程材料体积上的信号线，在信号线上共形形成的第一电介质材料，形成的不同的第二电介质材料 在第一电介质材料上，以及通过第一介电材料和第二介电材料形成的接触到信号线的接触。

    Anti-fuse based programmable serial number generator
    25.
    发明授权
    Anti-fuse based programmable serial number generator 有权
    基于反熔丝的可编程序列号发生器

    公开(公告)号：US08350356B2

    公开(公告)日：2013-01-08

    申请号：US12979265

    申请日：2010-12-27

    Applicant: Daniel Xu

    Inventor： Daniel Xu

    IPC: H01L27/06

    CPC classification number: H01L27/0629 ,  H01L27/092

    Abstract: An anti-fuse apparatus includes a substrate of a first conductivity type and a well region of a second conductivity type formed in the substrate. A junction between the well region and the substrate is characterized by a breakdown voltage higher than a predetermined voltage. The apparatus includes a contact region of the second conductivity type within the well region. The apparatus also includes a channel region and a drain region within the substrate. A gate dielectric layer overlies the channel region and the contact region. A first polysilicon gate, the drain region, and the well region are associated with an MOS transistor. The apparatus also includes a second polysilicon gate overlying the gate dielectric layer which overlies the contact region. The contact region is configured to receive a first supply voltage and the second polysilicon gate is configured to receive a second supply voltage.

    Abstract translation: 反熔丝装置包括形成在基板中的第一导电类型的基板和第二导电类型的阱区。 阱区和衬底之间的接合点的特征在于高于预定电压的击穿电压。 该装置包括在该区域内的第二导电类型的接触区域。 该装置还包括衬底内的沟道区域和漏极区域。 栅介质层覆盖沟道区和接触区。 第一多晶硅栅极，漏极区域和阱区域与MOS晶体管相关联。 该装置还包括覆盖在接触区域上的栅极电介质层的第二多晶硅栅极。 接触区域被配置为接收第一电源电压，并且第二多晶硅栅极被配置为接收第二电源电压。

    ANTI-FUSE BASED PROGRAMMABLE SERIAL NUMBER GENERATOR
    26.
    发明申请
    ANTI-FUSE BASED PROGRAMMABLE SERIAL NUMBER GENERATOR 有权
    基于反熔丝的可编程序列号发生器

    公开(公告)号：US20120061765A1

    公开(公告)日：2012-03-15

    申请号：US12979265

    申请日：2010-12-27

    Applicant: Daniel Xu

    Inventor： Daniel Xu

    IPC: H01L27/06 ,  H01L21/8238

    CPC classification number: H01L27/0629 ,  H01L27/092

    Abstract: An anti-fuse apparatus includes a substrate of a first conductivity type and a well region of a second conductivity type formed in the substrate. A junction between the well region and the substrate is characterized by a breakdown voltage higher than a predetermined voltage. The apparatus includes a contact region of the second conductivity type within the well region. The apparatus also includes a channel region and a drain region within the substrate. A gate dielectric layer overlies the channel region and the contact region. A first polysilicon gate, the drain region, and the well region are associated with an MOS transistor. The apparatus also includes a second polysilicon gate overlying the gate dielectric layer which overlies the contact region. The contact region is configured to receive a first supply voltage and the second polysilicon gate is configured to receive a second supply voltage.

    Abstract translation: 反熔丝装置包括形成在基板中的第一导电类型的基板和第二导电类型的阱区。 阱区和衬底之间的接合点的特征在于高于预定电压的击穿电压。 该装置包括在该区域内的第二导电类型的接触区域。 该装置还包括衬底内的沟道区域和漏极区域。 栅介质层覆盖沟道区和接触区。 第一多晶硅栅极，漏极区域和阱区域与MOS晶体管相关联。 该装置还包括覆盖在接触区域上的栅极电介质层的第二多晶硅栅极。 接触区域被配置为接收第一电源电压，并且第二多晶硅栅极被配置为接收第二电源电压。

    Barrier material encapsulation of programmable material
    27.
    发明授权
    Barrier material encapsulation of programmable material 失效

    公开(公告)号：US07064344B2

    公开(公告)日：2006-06-20

    申请号：US10418548

    申请日：2003-04-17

    Applicant: Daniel Xu

    Inventor： Daniel Xu

    IPC: H01L29/06

    CPC classification number: H01L21/76897 ,  H01L23/525 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  Y10S438/90 ,  H01L2924/00

    Abstract: A method comprising forming as stacked materials on a substrate, a volume of programmable material and a signal line, conformably forming a first dielectric material on the stacked materials, forming a second dielectric material on the first material, etching an opening in the second dielectric material with an etchant that, between the first dielectric material and the second dielectric material, favors removal of the second dielectric material, and forming a contact in the opening to the stacked materials. An apparatus comprising a contact point formed on a substrate, a volume of programmable material formed on the contact point, a signal line formed on the volume of programmable material, a first dielectric material conformally formed on the signal line, a different second dielectric material formed on the first dielectric material, and a contact formed through the first dielectric material and the second dielectric material to the signal line.

    Forming tapered lower electrode phase-change memories
    29.
    发明授权
    Forming tapered lower electrode phase-change memories 有权
    形成锥形下电极相变存储器

    公开(公告)号：US06933516B2

    公开(公告)日：2005-08-23

    申请号：US10839499

    申请日：2004-05-05

    Applicant: Daniel Xu

    Inventor： Daniel Xu

    IPC: H01L45/00 ,  H01L47/00

    CPC classification number: H01L45/06 ,  G11C2213/52 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

    Abstract: A phase-change memory may have a tapered lower electrode coated with an insulator. The coated, tapered electrode acts as a mask for a self-aligned trench etch to electrically separate adjacent wordlines. In some embodiments, the tapered lower electrode may be formed over a plurality of doped regions, and isotropic etching may be used to taper the electrode as well as part of the underlying doped regions.

    Abstract translation: 相变存储器可以具有涂覆有绝缘体的锥形下电极。 涂覆的锥形电极用作用于自对准沟槽蚀刻的掩模，以电隔离相邻字线。 在一些实施例中，锥形下电极可以形成在多个掺杂区域上，并且各向同性蚀刻可以用于使电极逐渐变细以及部分下面的掺杂区域。

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