Abstract:
A processing circuit of a display panel, a display method and a display device are provided. The display panel is divided into a plurality of display regions. The processing circuit includes: a plurality of display control circuits corresponding to the plurality of display regions respectively; a sight line acquisition circuit configured to acquire a focused region of the display panel on which sight lines of human eyes are focused; and a control circuit configured to determine from the plurality of display regions a first display region overlapping the focused region and a second display region not overlapping the focused region, enable the display control circuit corresponding to the first display region to output first image data, and enable the display control circuit corresponding to the second display region to output second image data having a refresh rate smaller than the first image data.
Abstract:
A gate driving circuit, a driving method thereof, a gate driver, a display panel and a display apparatus. In the gate driving circuit, a pull-up sub-circuit is configured to control the potential of a pull-up node according to signals inputted from first, second, third, fourth and fifth signal terminals and the potential of a pull-down node; a reset sub-circuit is configured to reset the potential of the pull-up node according to a signal inputted from a reset terminal; a pull-down sub-circuit is configured to control the potential of the pull-down node according to a signal inputted from the fourth signal terminal, a signal outputted from an output terminal and the potential of the pull-up node; and an output sub-circuit is configured to control a signal outputted from the output terminal according to a signal inputted from the third signal terminal, the potential of the pull-down node and the potential of the pull-up node.
Abstract:
Embodiments of the present disclosure provide a pixel unit and a driving method thereof, a display panel and a driving method thereof, and a display apparatus. The pixel unit comprises a driving sub-circuit, a first switching sub-circuit, a second switching sub-circuit, and a light-emitting element. The driving sub-circuit has a first terminal electrically coupled to a first power supply terminal, and a second terminal electrically coupled to a first terminal of the light-emitting element. The first switching sub-circuit has an inputting terminal electrically coupled to a data line, an outputting terminal electrically coupled to an inputting terminal of the second switching sub-circuit, and a controlling terminal electrically coupled to a scanning line. The second switching sub-circuit has an outputting terminal electrically coupled to an inputting terminal of the driving sub-circuit.
Abstract:
A scan driving circuit and a driving method thereof, an array substrate and a display device are provided. The scan driving circuit includes a scan signal generating circuit, a plurality of scan lines and a plurality of switching circuits. The scan signal generating circuit includes a plurality of output terminals for respectively outputting scan signals; the plurality of scan lines respectively correspond to the plurality of output terminals of the scan signal generating circuit and are divided into a plurality of scan line groups, and each of the plurality of scan line groups includes at least two scan lines; the plurality of switching circuits respectively correspond to the plurality of scan line groups and are respectively disposed between the plurality of scan line groups and the plurality of output terminals.
Abstract:
The present disclosure relates to a shift register unit, a driving method thereof, a gate driver on array and a display apparatus. The shift register unit includes a clock control circuit (10), an output control circuit (20) and an output circuit (30). The shift register unit may input clock signals of different frequencies or different duty ratios to the output control circuit (20) and the output circuit (30) respectively via the clock control circuit (10), such that the output circuit (30) can input driving signals of different frequencies or different duty ratios to the pixel units via the output end (OUT) in order to adjust the charging time for each line of pixel units. As a result, the driving manner of the display apparatus by the gate driver on array is enriched, and the driving flexibility is improved.
Abstract:
A shift register unit, a driving method, a gate driver on array and a display device. The shift register unit includes: a first clock control circuit, a second clock control circuit, an output control circuit and an output circuit. The first clock control circuit is configured to, under control of a second control signal from a second control signal terminal, a third clock signal from a third clock signal terminal, and a fourth clock signal from a fourth clock signal terminal, alternately output a second clock signal from a second clock signal terminal and a first clock signal from a first clock signal terminal to the output control circuit. The second clock control circuit is configured to alternately output the first clock signal and the second control signal to the output circuit under control of the second control signal, the third clock signal and the fourth clock signal.
Abstract:
A shift register unit, a driving method, a gate driver on array and a display device. The shift register unit includes: a first clock control circuit, a second clock control circuit, an output control circuit and an output circuit. The first clock control circuit is configured to, under control of a second control signal from a second control signal terminal, a third clock signal from a third clock signal terminal, and a fourth clock signal from a fourth clock signal terminal, alternately output a second clock signal from a second clock signal terminal and a first clock signal from a first clock signal terminal to the output control circuit. The second clock control circuit is configured to alternately output the first clock signal and the second control signal to the output circuit under control of the second control signal, the third clock signal and the fourth clock signal.
Abstract:
A color filter array substrate, a method for fabricating the same and a display device are disclosed. The color filter array substrate includes a plurality of gate lines and a plurality of data lines disposed as intersecting each other horizontally and vertically and a plurality of pixel regions defined by the gate lines and the data lines, each of the pixel regions includes a TFT, wherein each of the pixel regions further includes a band-pass filter layer, the band-pass filter layer transmits light within a specific wavelength range while reflects light of other wavelengths; the band-pass filter layer comprises a first medium sub-layer, a second medium sub-layer and a third medium sub-layer, the second medium layer is of different thicknesses at different pixel regions.
Abstract:
A color filter substrate, an array substrate, a liquid crystal panel and a liquid crystal display device are disclosed. Said color filter substrate includes a plurality of pixel units, wherein said pixel unit comprises two diamond shaped sub-pixels and four isosceles triangle shaped sub-pixels, every two isosceles triangle shaped sub-pixels are arranged into a sub-pixel column with their vertex angles opposite to each other, and two sub-pixel columns are parallel to each other; said two diamond shaped sub-pixels and said two sub-pixel columns are disposed alternatively in horizontal direction; and colors of said diamond sub-pixels and the isosceles triangle shaped sub-pixels at least contains red, blue and green. The liquid crystal panel can enhance color reproducibility of the liquid crystal display panel and refinement degree of picture display and hence improving reality of picture display effect.