公开(公告)号：US09437139B2

公开(公告)日：2016-09-06

申请号：US14362004

申请日：2013-10-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Danna Song ,  Liye Duan ,  Zhongyuan Wu ,  Cuili Gai

IPC: G09G5/10 ,  G09G3/32

CPC classification number: G09G3/3258 ,  G09G3/3233 ,  G09G2310/0248 ,  G09G2310/0291 ,  G09G2320/0242 ,  G09G2320/0295 ,  G09G2320/045 ,  G09G2330/028

Abstract: A pixel driving current extracting apparatus and a pixel driving current extracting method, the pixel driving current extracting apparatus comprises driving current extracting circuits corresponding to pixel driving circuits for respective colors respectively. Each of the driving current extracting circuits comprises a driving current amplifying and converting unit connected to the pixel driving circuit, for amplifying and converting a driving current of the pixel driving circuit into a voltage signal. A driving current computing unit connected to the driving current amplifying and converting unit is used for computing a pixel driving current according to the voltage signal. An amplification ratio of the driving current amplifying and converting unit in the driving current extracting circuits corresponding to the pixel driving circuits for respective colors is inversely proportional to a magnitude of the pixel driving current for respective colors. The pixel driving currents for respective colors are extracted uniformly and amplified properly without being distorted, thereby providing a well data support for the subsequent signal processing.

Abstract translation: 像素驱动电流提取装置和像素驱动电流提取方法，像素驱动电流提取装置包括分别对应于各个颜色的像素驱动电路驱动电流提取电路。 每个驱动电流提取电路包括连接到像素驱动电路的驱动电流放大和转换单元，用于将像素驱动电路的驱动电流放大并转换为电压信号。 连接到驱动电流放大和转换单元的驱动电流计算单元用于根据电压信号计算像素驱动电流。 与各颜色的像素驱动电路对应的驱动电流提取电路中的驱动电流放大和转换单元的放大率与各种颜色的像素驱动电流的大小成反比。 各颜色的像素驱动电流被均匀提取并被正确地放大而不会失真，从而为随后的信号处理提供良好的数据支持。

公开(公告)号：US20150255031A1

公开(公告)日：2015-09-10

申请号：US14366534

申请日：2013-12-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Kun Cao ,  Zhongyuan Wu ,  Liye Duan

IPC: G09G3/36

CPC classification number: G09G3/3648 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/067 ,  G09G2320/043 ,  G11C19/28

Abstract: Provided are a shift register unit and a gate driver circuit, which are configured to suppress output errors caused by the drifts in the threshold voltages and the interval existed in the operation of pulling the output terminal, and thus to enhance stability of the shift register unit. The shift register unit comprises: an input module, a first output module, a pull-down driving module, a pull-down module and a first output discharging unit. The pull-down driving module is connected to the first clock signal input terminal and the second clock signal input terminal, and configured to provide the first clock signal to a first pull-down node in response to the first clock signal, provide the second clock signal to a second pull-down node in response to the second clock signal, provide a first low voltage signal to the first pull-down node and the second pull-down node in response to the voltage signal at the pull-up node, provide the first low voltage signal to the second pull-down node in response to a voltage signal at the first pull-down node, and provide the first low voltage signal to the first pull-down node in response to a voltage signal at the second pull-down node.

Abstract translation: 提供了一种移位寄存器单元和栅极驱动器电路，其被配置为抑制由阈值电压中的漂移和拉动输出端子的操作中存在的间隔引起的输出误差，从而增强移位寄存器单元的稳定性 。 移位寄存器单元包括：输入模块，第一输出模块，下拉驱动模块，下拉模块和第一输出放电单元。 下拉驱动模块连接到第一时钟信号输入端和第二时钟信号输入端，并被配置为响应于第一时钟信号将第一时钟信号提供给第一下拉节点，提供第二时钟 响应于第二时钟信号向第二下拉节点发送信号，响应于上拉节点处的电压信号向第一下拉节点和第二下拉节点提供第一低电压信号，提供 所述第一低电压信号响应于所述第一下拉节点处的电压信号而被提供给所述第二下拉节点，并且响应于所述第二拉动期间的电压信号将所述第一低电压信号提供给所述第一下拉节点 下降节点。

公开(公告)号：US09013846B2

公开(公告)日：2015-04-21

申请号：US14074914

申请日：2013-11-08

Applicant: BOE Technology Group Co., Ltd.

Inventor： Liye Duan ,  Zhongyuan Wu

IPC: H02H9/04 ,  G02F1/1362

CPC classification number: H02H9/044 ,  G02F1/136204 ,  H02H9/046

Abstract: The invention discloses an ESD protection circuit and a method for driving the same and a display panel. The ESD protection circuit in the present invention comprises: a first TFT with a drain connected to a data signal line, a source and a gate connected together as a node; a second TFT with a drain connected to a first power supply line, a source connected to the data signal line, and a gate connected to the node; a third TFT with a drain connected to the data signal line, a source connected to a second power supply line, and a gate connected to a third power supply line; a forth TFT with a drain connected to the node, a source and a gate connected to the second power supply line; and a bootstrap capacitor connected between the node and the data signal line.

Abstract translation: 本发明公开了一种ESD保护电路及其驱动方法及显示面板。 本发明的ESD保护电路包括：第一TFT，漏极连接到数据信号线，源极和栅极连接在一起作为节点; 第二TFT，漏极连接到第一电源线，连接到数据信号线的源和连接到节点的栅极; 第三TFT，漏极连接到数据信号线，连接到第二电源线的源极和连接到第三电源线的栅极; 具有连接到节点的漏极的第四TFT，连接到第二电源线的源极和栅极; 以及连接在节点和数据信号线之间的自举电容器。

公开(公告)号：US20140362130A1

公开(公告)日：2014-12-11

申请号：US14355470

申请日：2013-12-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Liye Duan ,  Lirong Wang ,  Zhongyuan Wu

IPC: G09G3/32

CPC classification number: G09G3/3225 ,  G09G3/3241 ,  G09G2310/0262 ,  G09G2320/045

Abstract: Disclosed are a pixel circuit, a driving method thereof and a pixel array structure. The pixel circuit comprises a load controlling module(101), a load module(102), a gray scale selection module(103), a driving module(104) and a light-emitting device(105). The load controlling module(101) outputs an analog data signal through a first node and a second node under the control of a first scan signal (scan1). The load module(102) is connected with a first power supply terminal(VSS), the driving module(104), the first node(A1) and the second node(A2), respectively, and stores the analog data signal in the load module(102) and provides the driving module(104) with the analog data signal under the control of signals from the first node and the second node. The gray scale selection module(103) transmits a digital data signal to a third node(A3) located in the gray scale selection module(103) under the control of a second scan signal (scan2). The driving module(104) drives the light-emitting device(105) under the control of the signals from the second node and the third node. A first terminal of the light-emitting device(105) is connected with a second power supply terminal(VDD), a second terminal thereof is connected with the driving module(104). The pixel circuit is capable of reducing a charging time of an OLED pixel circuit.

Abstract translation: 公开了像素电路，其驱动方法和像素阵列结构。 像素电路包括负载控制模块（101），负载模块（102），灰度级选择模块（103），驱动模块（104）和发光装置（105）。 负载控制模块（101）在第一扫描信号（scan1）的控制下通过第一节点和第二节点输出模拟数据信号。 负载模块（102）分别与第一电源端子（VSS），驱动模块（104），第一节点（A1）和第二节点（A2）连接，并将模拟数据信号存储在负载 模块（102）并且在来自第一节点和第二节点的信号的控制下向驱动模块（104）提供模拟数据信号。 灰度级选择模块（103）在第二扫描信号（scan2）的控制下，将数字数据信号发送到位于灰度级选择模块（103）中的第三节点（A3）。 驱动模块（104）在来自第二节点和第三节点的信号的控制下驱动发光设备（105）。 发光装置（105）的第一端子与第二电源端子（VDD）连接，其第二端子与驱动模块（104）连接。 像素电路能够减少OLED像素电路的充电时间。

公开(公告)号：US12211448B2

公开(公告)日：2025-01-28

申请号：US17779164

申请日：2021-03-29

Applicant: Hefei BOE Joint Technology Co.,Ltd. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhidong Yuan ,  Pan Xu ,  Yongqian Li ,  Can Yuan ,  Zhongyuan Wu

IPC: G11C19/00 ,  G09G3/32 ,  G09G3/3266 ,  G11C19/28

Abstract: A display panel includes sub-pixels and a scan driving circuit. The scan driving circuit includes a plurality of stages of shift registers including at least one first shift register and at least one second shift register, and a plurality of clock signal lines including at least one first sub-clock signal line and at least one second sub-clock signal line. Each shift register includes a first sub-circuit and a second sub-circuit. A first sub-clock signal line in the at least one first sub-clock signal line is electrically connected to a first sub-circuit in a first shift register in the at least one first shift register. A second sub-clock signal line in the at least one second sub-clock signal line is electrically connected to one sub-circuit of a first sub-circuit and a second sub-circuit in a second shift register in the at least one second shift register.

公开(公告)号：US11844255B2

公开(公告)日：2023-12-12

申请号：US17040606

申请日：2019-12-20

Applicant: Hefei BOE Joint Technology Co., Ltd. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhongyuan Wu ,  Yongqian Li ,  Zhidong Yuan ,  Meng Li ,  Can Yuan

IPC: H10K59/131 ,  H10K59/122 ,  H10K50/86 ,  H10K50/828 ,  H10K59/124 ,  H10K50/824 ,  H10K59/12 ,  H10K71/00 ,  H10K102/10 ,  H10K102/00

CPC classification number: H10K59/1315 ,  H10K50/824 ,  H10K50/828 ,  H10K50/865 ,  H10K59/122 ,  H10K59/124 ,  H10K59/131 ,  H10K71/00 ,  H10K59/1201 ,  H10K2102/102 ,  H10K2102/103 ,  H10K2102/3026

Abstract: A display panel includes a substrate, a pad, an auxiliary electrode layer, a data line layer, a first electrode layer, a light emitting layer, and a second electrode layer. The substrate has a display area and a peripheral area. The pad is disposed on a side of the substrate and located in the peripheral area. The auxiliary electrode layer is disposed on the same side of the substrate as the pad; the data line layer is disposed on a same layer as the auxiliary electrode layer; the first electrode layer is disposed on a side of the auxiliary electrode layer facing away from the substrate; the light emitting layer is disposed on a side of the first electrode layer facing away from the substrate; and the second electrode layer is disposed on a side of the light emitting layer facing away from the substrate and connected to the auxiliary electrode layer.

公开(公告)号：US11238793B2

公开(公告)日：2022-02-01

申请号：US16712045

申请日：2019-12-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Song Meng ,  Zhongyuan Wu

IPC: G09G3/3233 ,  G09G3/3225

Abstract: A pixel compensation method includes: detecting driving transistors of pixels to obtain present characteristic values of the driving transistors of the pixels; extracting historical compensation characteristic values of the driving transistors of the pixels obtained in a previous display cycle of a screen; calculating a present compensation characteristic value of at least one driving transistor of the pixels according to a present characteristic value and a historical compensation characteristic value corresponding to the driving transistor of the pixels; and compensating a corresponding pixel according to the present compensation characteristic value of the driving transistor of the pixels.

公开(公告)号：US11127350B2

公开(公告)日：2021-09-21

申请号：US16071667

申请日：2017-08-02

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Cuili Gai ,  Zhongyuan Wu ,  Baoxia Zhang ,  Ling Wang ,  Yicheng Lin ,  Quanhu Li ,  Fang Liu

IPC: G06F3/038 ,  G09G5/00 ,  G09G3/3258 ,  G09G3/3233 ,  G09G3/3291

Abstract: A pixel circuit includes a first transistor having a bottom gate and a top gate, a drain supplied with a high-level power-supply voltage, and a source coupled to a light-emitting diode (LED). The bottom gate is provided with a first voltage signal and the source is provided with a second voltage signal in a compensation period during which a present value of a threshold voltage of the first transistor is sensed at the source and a third voltage signal is determined based on the present value of the threshold voltage. The top gate is configured to be provided with the third voltage signal in an emission period to reduce the present value of the threshold voltage.

公开(公告)号：US11011114B2

公开(公告)日：2021-05-18

申请号：US16335009

申请日：2018-08-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Song Meng ,  Zhongyuan Wu ,  Danna Song

IPC: G09G3/3258 ,  G09G3/20

Abstract: The present disclosure provides a compensation method, device, circuit for a display panel, a display panel and a display device. The display panel includes a plurality of pixel circuits, each of which comprises a driving transistor. The compensation method includes: obtaining a first compensation grayscale value GL1 and a second compensation grayscale value GL2 of a pixel circuit to be compensated; obtaining a first compensation luminance L1, a first gate-source voltage Vgs1 of the driving transistor, a second compensation luminance L2, and a second gate-source voltage Vgs2 of the driving transistor, wherein L1 and Vgs1 correspond to GL1, and L2 and Vgs2 correspond to GL2; obtaining a theoretical luminance L corresponding to an input grayscale value GL; calculating the compensation gate-source voltage V′gs by using L, L1, Vgs1, L2, and Vgs2; and obtaining an output compensation grayscale value GL′ according to V′gs.

公开(公告)号：US10439630B2

公开(公告)日：2019-10-08

申请号：US15766085

申请日：2017-09-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chen Song ,  Song Meng ,  Danna Song ,  Zhongyuan Wu

IPC: H03M1/12 ,  H03M1/50 ,  G09G3/00 ,  H03M1/10 ,  G09G3/3233

Abstract: The present application discloses an analog-to-digital conversion (ADC) circuit. The circuit includes an integral circuit including an operational amplifier and an integral capacitor. The circuit further includes a comparator and a timer. The operational amplifier includes a positive input terminal configured to receive a first voltage, a negative input terminal coupled to a signal-collection line configured to collect an analog current signal, and an output terminal configured to output a first output signal. The comparator is configured to compare the first output signal with a second voltage to generate a second output signal to the timer. The timer is configured to start a timing operation when the operational amplifier receives the analog current signal and end the timing operation when the second output signal changes. A binary data resulted from the timing operation characterizes a digital signal corresponding to the analog current signal.