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公开(公告)号：US20220293018A1
公开(公告)日：2022-09-15
申请号：US17508866
申请日：2021-10-22
Applicant: BOE Technology Group Co., Ltd.
Inventor： Shuilang DONG , Xinhong LU , Jingshang ZHOU , Lei ZHAO , Zhanfeng CAO , Dapeng XUE , Lizhong WANG , Guangcai YUAN
Abstract: The present application discloses an array substrate and a splicing screen. The array substrate provided by an embodiment of the present application includes: a flexible base, wherein the flexible base includes a display region, a first region and a second region, the display region and at least one of the first region and the second region are located in different planes, and the first region is located between the display region and the second region; a plurality of signal lines, arranged on the display region and the first region; a plurality of fan-out lines, arranged on the second region and connected with the plurality of signal lines in a one-to-one correspondence; and a buffer cushion, arranged on the first region, wherein an orthographic projection of the buffer cushion on the flexible base does not overlap with orthographic projections of the signal lines on the flexible base.
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公开(公告)号：US20220255025A1
公开(公告)日：2022-08-11
申请号：US17732781
申请日：2022-04-29
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Wei YANG , Guangcai YUAN , Ce NING , Xinhong LU , Tianmin ZHOU , Xin YANG
Abstract: The present disclosure relates to an OLED display panel and display device. The OLED display panel includes: a display area, a bending area and a bonding area for bonding a circuit board, wherein the display panel further includes: a base substrate; a first semiconductor pattern on the base substrate; a first insulating layer group on the first semiconductor pattern; a second semiconductor pattern on the first insulating layer group; a second insulating layer group on the second semiconductor pattern; first via holes in the first insulating layer group and the second insulating layer group; second via holes in the second insulating layer group, wherein the display panel further includes: a first groove located in the bending area and having a depth substantially identical to that of the first via holes; and a metal trace, connecting a trace in the display area to the circuit board.
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23.发明申请公开(公告)号：US20190267409A1
公开(公告)日：2019-08-29
申请号：US16302850
申请日：2018-03-13
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Hehe HU , Wei YANG , Xinhong LU , Ke WANG , Yu WEN
IPC: H01L27/12 , H01L29/786 , H01L29/66
Abstract: Embodiment of the present disclosure provide a thin-film transistor structure, a manufacturing method thereof, a display panel and a display device. The thin-film transistor structure includes: a base substrate; and a first thin-film transistor and a second thin-film transistor formed on the base substrate, wherein a first active layer of the first thin-film transistor is doped with hydrogen; a material of a second active layer of the second thin-film transistor is metal oxide; and a first isolation barrier surrounding the first thin-film transistor and/or a second isolation barrier surrounding the second thin-film transistor are disposed on the base substrate.
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公开(公告)号：US20240304136A1
公开(公告)日：2024-09-12
申请号：US18664242
申请日：2024-05-14
Applicant: BOE Technology Group Co., Ltd.
Inventor： Hao CHEN , Zhenyu ZHANG , Jiao ZHAO , Li XIAO , Dongni LIU , Haoliang ZHENG , Liang CHEN , Minghua XUAN , Ming YANG , Xinhong LU , Qi QI
CPC classification number: G09G3/32 , G01R31/52 , G01R31/54 , G09G3/006 , G09G3/035 , H01L25/0753 , H01L27/1244 , H01L33/62 , G09F9/33 , G09G2300/0426 , G09G2300/0452 , G09G2320/0233 , G09G2330/021
Abstract: Disclosed are an array substrate, a detection method for the array substrate, and a splicing display panel. In the array substrate, each of pixels (1) includes sub-pixels (01) of at least three colors and a pixel driving chip (02) for driving each sub-pixel (01) to emit light; each sub-pixel (01) includes at least one inorganic light-emitting diode; a display area (A1) further includes: a positive signal line (Hm) connected to a positive electrode of each inorganic light-emitting diode, and a data signal line (Dm), a scanning line (Sn), and a reference signal line (Vm) connected to each pixel driving chip (02); each pixel driving chip (02) is used for writing signals of the data signal line (Dm) into the sub-pixels (01) of different colors under the control of the corresponding scanning line (Sn) in a time division manner.
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公开(公告)号：US20240282782A1
公开(公告)日：2024-08-22
申请号：US18640015
申请日：2024-04-19
Applicant: BOE Technology Group Co., Ltd.
Inventor： Guoteng LI , Shuilang DONG , Xinhong LU , Jingshang ZHOU , Liuqing LI , Zhao CUI , Dapeng XUE , Zhiqiang XU , Jintao PENG , Weixing LIU , Kai GUO , Chunfang ZHANG , Meirong LU , Wanpeng TENG
CPC classification number: H01L27/1248 , H01L25/167
Abstract: A display panel and a display device are provided. The display panel includes a plurality of display units, each display unit includes a transparent area, and the display panel further includes a base substrate and a composite functional layer. The composite functional layer is provided on a side of the base substrate and has a first through-hole formed therein, and the first through-hole is provided in the transparent area. The composite functional layer includes a composite transparent layer and a light-shielding layer. The composite transparent layer includes a plurality of transparent functional layers, and includes a light-transmitting part surrounding the first through-hole. An orthographic projection of the light-shielding layer on the base substrate covers an orthographic projection of at least a portion of the light-transmitting part on the base substrate.
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Patent Agency Ranking
公开(公告)号：US20220393087A1
公开(公告)日：2022-12-08
申请号：US17775959
申请日：2021-05-20
Inventor： Ting ZENG , Xinhong LU , Heren GUI , Jian YANG , Yongfei LI
Abstract: The present disclosure provides a display substrate, including: a base substrate including a display area and a bonding area; a first metal conductive layer pattern on the base substrate; a first passivation layer on the first metal conductive layer pattern; a second metal conductive layer pattern on the first passivation layer; a second passivation layer on the second metal conductive layer pattern; a first blackening layer pattern is disposed between the first metal conductive layer pattern and the first passivation layer, an orthographic projection of which on the base substrate is located in that of the first metal conductive layer pattern on the base substrate; and/or a second blackening layer pattern is disposed between the second metal conductive layer pattern and the second passivation layer, an orthographic projection of which on the base substrate is located in that of the second metal conductive layer pattern on the base substrate.
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公开(公告)号：US20220250870A1
公开(公告)日：2022-08-11
申请号：US17631090
申请日：2021-04-09
Applicant: BOE Technology Group Co., Ltd.
Inventor： Shuqi LIU , Xinhong LU , Wenyue FU , Haoran GAO , Guangcai YUAN , Li LI , Shaodong SUN , Song FANG , Dongfeng DU , Qi QI
Abstract: A folding device is provided, The folding device includes a bearing and fixing mechanism (1) configured to bear and fix a main body portion (21) of a to-be-folded device (2); a folding mechanism (3) located on at least one side of the bearing and fixing mechanism (1), the folding mechanism (3) being rotatably connected to the bearing and fixing mechanism (1) and configured to bear and fix a to-be-folded portion (22) of the to-be-folded device (2); and a driving mechanism (4) connected to the folding mechanism (3), the driving mechanism (4) being configured to drive the folding mechanism (3) to turn relative to the bearing and fixing mechanism (1), so as to fold the to-be-folded portion (22) to a side in a thickness direction of the main body portion (21), The folding device can fold automatically, and manual folding is avoided.
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公开(公告)号：US20210408331A1
公开(公告)日：2021-12-30
申请号：US16959097
申请日：2019-08-16
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zhiwei LIANG , Yingwei LIU , Han YUE , Minghua XUAN , Hsuanwei MAI , Zhanfeng CAO , Ke WANG , Huijuan WANG , Guangcai YUAN , Zhijun LV , Xinhong LU
Abstract: A display backplane includes a base, a plurality of driving electrodes disposed above the base, and a connection structure disposed on at least one of the plurality of driving electrodes. An orthographic projection of the connection structure on the base is within an orthographic projection of a corresponding driving electrode on the base; and the connection structure includes at least one conductive portion disposed at a first included angle with the corresponding driving electrode.
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公开(公告)号：US20210280615A1
公开(公告)日：2021-09-09
申请号：US17328393
申请日：2021-05-24
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Wei YANG , Xinhong LU
IPC: H01L27/12 , H01L29/66 , H01L29/786
Abstract: A display device is disclosed. The display device includes a display area and a wiring area. The display area is disposed with a first thin film transistor which is an oxide thin film transistor and a second thin film transistor which is a low temperature poly-silicon thin film transistor. A distance between a first active layer of the first thin film transistor and a substrate is different from a distance between a second active layer of the second thin film transistor and the substrate. The first thin film transistor includes first vias that receive a first source/drain. The second thin film transistor includes second vias that receives a second source/drain. The wiring area is provided with a groove. The groove includes a first sub-groove and a second sub-groove that are stacked, and depths of the second vias are substantially equal to a depth of the second sub-groove.
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公开(公告)号：US20210225893A1
公开(公告)日：2021-07-22
申请号：US16765216
申请日：2019-12-06
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Wei YANG , Guangcai YUAN , Ce NING , Xinhong LU , Tianmin ZHOU , Xin YANG
IPC: H01L27/12
Abstract: A method of manufacturing an array substrate includes: forming a first semiconductor pattern and a first insulating layer group sequentially on a base substrate; forming a second semiconductor pattern and a second insulating layer group sequentially on the first insulating layer group; forming two first via holes in the first insulating layer group and the second insulating layer group to expose the first semiconductor pattern, annealing the exposed first semiconductor pattern and then removing an oxide layer on a surface of the first semiconductor pattern; forming connecting wires in the first via holes; forming second via holes in the second insulating layer group to expose the second semiconductor pattern, and forming a first source electrode and a first drain electrode in the second via holes such that the first source electrode or the first drain electrode covers and is connected to one of the connecting wires.
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