公开(公告)号：US20220255025A1

公开(公告)日：2022-08-11

申请号：US17732781

申请日：2022-04-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wei YANG ,  Guangcai YUAN ,  Ce NING ,  Xinhong LU ,  Tianmin ZHOU ,  Xin YANG

IPC: H01L51/00 ,  H01L27/32

Abstract: The present disclosure relates to an OLED display panel and display device. The OLED display panel includes: a display area, a bending area and a bonding area for bonding a circuit board, wherein the display panel further includes: a base substrate; a first semiconductor pattern on the base substrate; a first insulating layer group on the first semiconductor pattern; a second semiconductor pattern on the first insulating layer group; a second insulating layer group on the second semiconductor pattern; first via holes in the first insulating layer group and the second insulating layer group; second via holes in the second insulating layer group, wherein the display panel further includes: a first groove located in the bending area and having a depth substantially identical to that of the first via holes; and a metal trace, connecting a trace in the display area to the circuit board.

公开(公告)号：US20210225893A1

公开(公告)日：2021-07-22

申请号：US16765216

申请日：2019-12-06

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wei YANG ,  Guangcai YUAN ,  Ce NING ,  Xinhong LU ,  Tianmin ZHOU ,  Xin YANG

IPC: H01L27/12

Abstract: A method of manufacturing an array substrate includes: forming a first semiconductor pattern and a first insulating layer group sequentially on a base substrate; forming a second semiconductor pattern and a second insulating layer group sequentially on the first insulating layer group; forming two first via holes in the first insulating layer group and the second insulating layer group to expose the first semiconductor pattern, annealing the exposed first semiconductor pattern and then removing an oxide layer on a surface of the first semiconductor pattern; forming connecting wires in the first via holes; forming second via holes in the second insulating layer group to expose the second semiconductor pattern, and forming a first source electrode and a first drain electrode in the second via holes such that the first source electrode or the first drain electrode covers and is connected to one of the connecting wires.

公开(公告)号：US20200058691A1

公开(公告)日：2020-02-20

申请号：US16542441

申请日：2019-08-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Rui HUANG ,  Xin YANG ,  Tianmin ZHOU ,  Huili WU

IPC: H01L27/146

Abstract: A photoelectric detection substrate, a method for fabricating the same, and a photoelectric detection device are disclosed. The photoelectric detection substrate includes a thin film transistor and a photodiode coplanar with the thin film transistor. The thin film transistor has a vertical channel structure and includes a gate electrode, an active layer, a first electrode and a second electrode. The photodiode includes a first doped layer, an absorption layer and a second doped layer disposed in this order. The active layer and the absorption layer are disposed in a same layer and formed by a same patterning process. By forming a photodiode coplanar with a thin film transistor of a vertical channel structure, the overall thickness of the photoelectric detection substrate is effectively reduced, deformation of the substrate caused by stress is reduced, and damage caused by deformation of the substrate is avoided, and thereby the yield is improved.

公开(公告)号：US20190172931A1

公开(公告)日：2019-06-06

申请号：US16094149

申请日：2018-03-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xin YANG

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/786

Abstract: A thin film transistor and a manufacturing method thereof, an array substrate and a display panel are provided, and the manufacturing method includes: forming an amorphous silicon layer on a base substrate, and simultaneously doping a first predetermined element into the amorphous silicon layer; converting the amorphous silicon layer including the first predetermined element into a polysilicon layer which includes a channel region serving as a channel of the thin film transistor, a first region located at a side of the channel region and configured to be connected with a source electrode, and a second region located at another side of the channel region and configured to be connected with a drain electrode; and implanting a second predetermined element into the first region and the second region by an ion implantation process to form a doped source region and a doped drain region, respectively.