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公开(公告)号：US11036090B2
公开(公告)日：2021-06-15
申请号：US15258161
申请日：2016-09-07
Inventor： Xiaoyuan Wang , Wu Wang , Rui Wang , Yajie Bai , Zhuo Xu
IPC: H01L27/32 , G02F1/1339 , G02F1/1343
Abstract: Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, and a display device. The array substrate has a display region and a wiring region located on a periphery of the display region. The array substrate includes a base substrate, and a transparent conductive strip and a wire formed on the base substrate in the wiring region; the transparent conductive strip and the wire are located in different layers and are in direct contact with each other, and the wire has one or more exposure holes formed therein.
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公开(公告)号：US10379276B2
公开(公告)日：2019-08-13
申请号：US16122022
申请日：2018-09-05
Abstract: A display device and a method for forming the same are provided. The display device includes a backlight module, a display panel, an optical film, and a cladding layer arranged in a stack-up manner. The cladding layer is configured to fix the backlight module and the display panel. The cladding layer includes a first portion and a second portion. The first portion is at a light-emitting side of the display panel, at least a part of the first portion is located between the display panel and the optical film, and the second portion is a lateral surface of the backlight module.
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公开(公告)号：US10043461B2
公开(公告)日：2018-08-07
申请号：US14740661
申请日：2015-06-16
Abstract: The present invention provides a shift register unit, a gate driving circuit and a display device. The shift register unit comprises a pull-up module, an output module and a pull-down module. The output module comprises a plurality of output lines, and a driving transistor is arranged on each output line. A switching device is arranged on at least one output line and used for turning on or turning off the output line.
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24.发明授权公开(公告)号：US09991348B2
公开(公告)日：2018-06-05
申请号：US15305826
申请日：2016-02-15
Inventor： Zhuo Xu , Jaikwang Kim , Rui Wang , Yajie Bai
IPC: H01L29/417 , H01L27/12 , G02F1/1368 , G02F1/1362 , G02F1/1343 , G09G3/36
CPC classification number: H01L29/41733 , G02F1/134309 , G02F1/136286 , G02F1/1368 , G02F2201/123 , G02F2201/40 , G09G3/3648 , G09G3/3655 , G09G2300/043 , G09G2320/0247 , H01L21/77 , H01L27/12 , H01L27/124 , H01L27/1259
Abstract: An array substrate includes a gate electrode and a source electrode arranged on a base substrate of the array substrate. The source electrode has a first end connected to a pixel electrode on the array substrate, and a second end opposite to the first end. A tip of the second end is provided with an extension portion, and an orthogonal projection of the extension portion onto the base substrate extends beyond an orthogonal projection of the gate electrode onto the base substrate.
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公开(公告)号：US09905626B2
公开(公告)日：2018-02-27
申请号：US14802807
申请日：2015-07-17
IPC: H01L25/16 , H01L51/50 , H01L23/528 , H01L23/522 , H01L27/32 , G02F1/1362
CPC classification number: H01L27/3276 , G02F1/136286 , H01L25/167 , H01L2251/5315 , H01L2924/0002 , H01L2924/00
Abstract: Embodiments of the present invention provide an array substrate, a display panel and a display apparatus. They relate to the technical field of display technologies and can prevent the peripheral signal wirings of a display region from occupying non-display regions on both sides additionally. In this way, when the array substrate is applied in the display panel, the frame on both sides of the display region on the display panel may be omitted. The array substrate includes: a base substrate; signal lines located in positions on the base substrate corresponding to a display region of the array substrate; a pattern layer, in which the signal lines are arranged; and signal line wirings located between the pattern layer and the base substrate, wherein the signal line wirings are configured to input signals into the signal lines.
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Patent Agency Ranking
公开(公告)号：US20170205673A1
公开(公告)日：2017-07-20
申请号：US15107083
申请日：2015-12-10
IPC: G02F1/1362 , G02F1/133 , G02F1/1368 , G02F1/1343
CPC classification number: G02F1/136213 , G02F1/13306 , G02F1/134309 , G02F1/136259 , G02F1/136286 , G02F1/1368 , G02F2201/121 , G02F2201/123 , G02F2201/506
Abstract: The present disclosure provides an array substrate comprising a plurality of data lines and a plurality of groups of gate lines, a display panel comprising the array substrate, a display device comprising the display panel and an electronic device comprising the display device. The plurality of data lines and the plurality of groups of gate lines intersect each other for dividing the array substrate into a plurality of pixel units. Each group of gate lines defines a row of a plurality of pixel units and comprises a first gate line and a second gate line. Each pixel unit comprises a first pixel electrode and a second pixel electrode, the first pixel electrode corresponds to the second gate line and the second pixel electrode corresponds to the first gate line. Each pixel unit comprises a first repair unit electrically coupled to the first pixel electrode and forming a first repair capacitance with the first gate line, and a second repair unit electrically coupled to the second pixel electrode and forming a second repair capacitance with the second gate line. Each pixel unit further comprises a main compensating unit electrically coupled to the first pixel electrode and forming a compensation capacitance with the second gate line.
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公开(公告)号：US12073787B2
公开(公告)日：2024-08-27
申请号：US18320042
申请日：2023-05-18
IPC: G09G3/3233
CPC classification number: G09G3/3233 , G09G2300/0426 , G09G2300/0842 , G09G2310/061 , G09G2320/0233 , G09G2320/0247
Abstract: A display panel includes pixel circuits, and the pixel circuit includes: a driving sub-circuit, a fourth sub-circuit and a first reset sub-circuit. The driving sub-circuit includes a driving transistor and a storage capacitor. The driving transistor includes a gate and an active pattern including a source portion and a drain portion. The storage capacitor includes a first storage electrode sharing a same electrode with the gate and a second storage electrode used to be connected to a first voltage signal line. The fourth sub-circuit is configured such that the drain portion and the gate are connected when being turned on. The first reset sub-circuit includes a first active pattern, which is arranged in a same layer as the active pattern and includes a first source portion being used to be connected to a first initialization signal line and a first drain portion being connected to the drain portion.
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公开(公告)号：US20240177657A1
公开(公告)日：2024-05-30
申请号：US17788581
申请日：2021-09-17
Inventor： Rui Wang , Chao Zeng , Ming Hu , Haijun Qiu , Weiyun Huang , Tianyi Cheng
IPC: G09G3/3225 , H10K59/131
CPC classification number: G09G3/3225 , H10K59/131 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842
Abstract: A pixel driving circuit is provided. The pixel driving circuit includes a driving transistor; a storage capacitor; a first reset transistor having a gate electrode connected to a first gate line in a present stage of a plurality of first gate lines, a source electrode connected to a respective first reset signal line of a plurality of first reset signal lines, and a drain electrode connected to an anode of a light emitting element; and a second reset transistor having a gate electrode connected to a first gate line in a previous stage of the plurality of first gate lines, a source electrode connected to a respective second reset signal line of a plurality of second reset signal lines, and a drain electrode connected to a drain electrode of the driving transistor.
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公开(公告)号：US11875713B2
公开(公告)日：2024-01-16
申请号：US17781288
申请日：2021-05-17
Inventor： Xianfeng Yuan , Jianjun Wang , Xiaoshi Liu , Junbo Xu , Rui Wang , Yuanyuan Liu , Xuanxuan Qiao
CPC classification number: G09G3/006 , H03H3/08 , G09G2310/0294 , G09G2310/08 , G09G2330/04
Abstract: An overcurrent protection circuit includes: a sampling sub-circuit configured to acquire gate input signals, select a gate input signal with a voltage value greater than a first preset voltage value as a sample gate input signal, generate a first control signal according to the sample gate input signal, and output the first control signal; a delay determination sub-circuit configured to receive the first control signal, delay the first control signal for a first preset time, determine whether a voltage value of the first control signal after delay is less than a voltage value of the first control signal before the delay, and if not, output a counting signal; and a counting control sub-circuit configured to receive the counting signal, perform counting according to the counting signal, and if a counted number reaches a preset number, output a second control signal.
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公开(公告)号：US11810506B2
公开(公告)日：2023-11-07
申请号：US17608746
申请日：2021-02-10
Inventor： Yao Huang , Rui Wang , Benlian Wang , Haigang Qing , Zhi Wang
IPC: G09G3/3233
CPC classification number: G09G3/3233 , G09G2300/0842 , G09G2310/061 , G09G2320/0233 , G09G2320/0247
Abstract: A pixel circuit, driving method for same and display apparatus are provided. The pixel circuit includes a driving sub-circuit, writing sub-circuit, compensation sub-circuit, first reset sub-circuit, first and second emitting control sub-circuits, and emitting element. The compensation sub-circuit writes signal of third node into first node under control of third scanning signal terminal, and compensates first node under control of the third scanning signal terminal and first voltage terminal. The first reset sub-circuit writes signal of first initial signal terminal into third node under control of first scanning signal terminal and first emitting control signal terminal. The second emitting control sub-circuit provides signal of first voltage terminal for second node under control of second emitting control signal terminal. The first emitting control sub-circuit provides signal of third node for fourth node under control of the first emitting control signal terminal, allows driving current to flow between third and fourth nodes.
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