公开(公告)号：US20190114433A1

公开(公告)日：2019-04-18

申请号：US16206092

申请日：2018-11-30

Applicant: Apple Inc.

Inventor： Joshua P. de Cesare ,  Timothy R. Paaske ,  Xeno S. Kovah ,  Nikolaj Schlej ,  Jeffrey R. Wilcox ,  Hardik K. Doshi ,  Kevin H. Alderfer ,  Corey T. Kallenberg

IPC: G06F21/57 ,  G06F21/62 ,  G06F9/4401 ,  G06F21/79

Abstract: A method and apparatus for protecting boot variables is disclosed. A computer system includes a main processor and an auxiliary processor. The auxiliary processor is associated with a non-volatile memory that stores variables associated with boot code that is also stored thereon. The main processor may send a request to the auxiliary processor to alter one of the variables stored in the non-volatile memory. Responsive to receiving the request, the auxiliary processor may execute a security policy to determine if the main processor meets the criteria for altering the variable. If the auxiliary processor determines that the main processor meets the criteria, it may grant permission to alter the variable.

公开(公告)号：US20190102558A1

公开(公告)日：2019-04-04

申请号：US16205838

申请日：2018-11-30

Applicant: Apple Inc.

Inventor： Joshua P. de Cesare ,  Timothy R. Paaske ,  Xeno S. Kovah ,  Nikolaj Schlej ,  Jeffrey R. Wilcox ,  Ezekiel T. Runyon ,  Hardik K. Doshi ,  Kevin H. Alderfer ,  Corey T. Kallenberg

IPC: G06F21/57 ,  G06F9/4401

Abstract: A method and apparatus for performing a secure boot of a computer system is disclosed. A computer system according to the disclosure includes an auxiliary processor and a main processor. The boot process includes initially booting the auxiliary processor. The auxiliary processor is associated with a non-volatile memory storing boot code for the main processor. The auxiliary processor may perform a verification of the boot code. Subsequent to verifying the boot code, the main processor may be released from a reset state. Once the main processor is no longer in the reset state, the boot code may be provided thereto. Thereafter, the boot procedure may continue with the main processor executing the boot code.

公开(公告)号：US20190026501A1

公开(公告)日：2019-01-24

申请号：US16128396

申请日：2018-09-11

Applicant: Apple Inc.

Inventor： Pierre-Olivier J. Martel ,  Jeffrey R. Wilcox ,  Ian P. Shaeffer ,  Andrew D. Myrick ,  Robert W. Hill ,  Tristan F. Schaap

IPC: G06F21/76 ,  G06F21/32

Abstract: Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuitry of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).

公开(公告)号：US20190012484A1

公开(公告)日：2019-01-10

申请号：US15748893

申请日：2016-08-25

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Joseph Sokol, Jr. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

IPC: G06F21/72 ,  G06F21/78 ,  G06F12/14 ,  G06F12/1027 ,  G06F12/02 ,  H04L9/08

CPC classification number: G06F21/72 ,  G06F12/0246 ,  G06F12/1027 ,  G06F12/1408 ,  G06F21/78 ,  G06F2212/7206 ,  G06F2212/7208 ,  G06F2221/2143 ,  H04L9/0861 ,  H04L9/0894 ,  H04L2209/12

Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

公开(公告)号：US20180349649A1

公开(公告)日：2018-12-06

申请号：US15720736

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Pierre-Olivier J. Martel ,  Jeffrey R. Wilcox ,  Ian P. Shaeffer ,  Andrew D. Myrick ,  Robert W. Hill ,  Tristan F. Schaap

IPC: G06F21/76 ,  G06F21/74 ,  G06F21/81

CPC classification number: G06F21/71 ,  G06F1/3237 ,  G06F1/3287 ,  G06F21/57 ,  G06F21/62 ,  G06F2221/2111 ,  G06F2221/2141 ,  G06F2221/2151 ,  H01L23/57 ,  H04L63/0861 ,  H04L63/107 ,  H04L63/108

Abstract: Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuity of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).