公开(公告)号：US20180013296A1

公开(公告)日：2018-01-11

申请号：US15714891

申请日：2017-09-25

Applicant: Apple Inc.

Inventor： Eric Smith ,  Bryan R. Hinch ,  Tommee So

IPC: H02J7/00 ,  G06F1/26

CPC classification number: H02J7/007 ,  G06F1/263 ,  Y10T307/858

Abstract: Circuits, methods, and apparatus that may allow an electronic device to control a power adapter. One example may provide an electronic system where an electronic device may control a power adapter through a communication channel. Data transferred in the communication channel may include the temperature of the power adapter, the charging capability of the adapter, and other types of data. In one example, power and data may share the same two wires, and the power and data may be time-division multiplexed. That is, the two wires may convey power and data at different times. Another example may include circuitry to detect a connection between the electronic device and the power adapter. Once a connection is detected, power may be transferred from the power adapter to the electronic device. This power transfer may be interrupted on occasion to transfer data between the power adapter to the electronic device.

公开(公告)号：US09774207B2

公开(公告)日：2017-09-26

申请号：US14487061

申请日：2014-09-15

Applicant: Apple Inc.

Inventor： Eric Smith ,  Bryan R. Hinch ,  Tommee So

IPC: H02J7/00 ,  G06F1/26

CPC classification number: H02J7/007 ,  G06F1/263 ,  Y10T307/858

Abstract: Circuits, methods, and apparatus that may allow an electronic device to control a power adapter. One example may provide an electronic system where an electronic device may control a power adapter through a communication channel. Data transferred in the communication channel may include the temperature of the power adapter, the charging capability of the adapter, and other types of data. In one example, power and data may share the same two wires, and the power and data may be time-division multiplexed. That is, the two wires may convey power and data at different times. Another example may include circuitry to detect a connection between the electronic device and the power adapter. Once a connection is detected, power may be transferred from the power adapter to the electronic device. This power transfer may be interrupted on occasion to transfer data between the power adapter to the electronic device.

公开(公告)号：US20250093932A1

公开(公告)日：2025-03-20

申请号：US18468467

申请日：2023-09-15

Applicant: Apple Inc.

Inventor： John G. DORSEY ,  Bryan R. Hinch ,  Ronit Banerjee ,  Karthic A. Palaniappan

IPC: G06F1/28

Abstract: Some embodiments include a system, apparatus, method, and computer program product for memory hierarchy power management. Some embodiments include a performance controller that balances memory hierarchy power and compute power to maintain package-level power efficiency of a systems-on-a-chip (SoC)-memory package. The performance controller can determine a ratio of memory hierarchy power to compute agent power, compare the ratio against a threshold value, and based on the comparison, determine how to manage memory hierarchy power. When the energy costs of the memory hierarchy power are large relative to the energy costs of the compute agent power, some embodiments include changing a performance state of a fabric and/or memory to increase the power efficiency of the overall SoC-memory package, even though a number of memory stall cycles experienced by the compute agent may increase.

公开(公告)号：US12147839B2

公开(公告)日：2024-11-19

申请号：US17392929

申请日：2021-08-03

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  Bryan R. Hinch ,  Ronit Banerjee ,  Kushal Dalmia ,  Daniel A. Chimene ,  Jaidev P. Patwardhan

IPC: G06F9/50 ,  G06F9/48 ,  G06F11/14

Abstract: Embodiments include an asymmetric multiprocessing (AMP) system having a first central processing unit (CPU) cluster comprising a first core type, and a second CPU cluster comprising a second core type, where the AMP system can update a thread metric for a first thread running on the first CPU cluster based at least on: a past shared resource overloaded metric of the first CPU cluster, and on-core metrics of the first thread. The on-core metrics can indicate that first thread contributes to contention of the same shared resource corresponding to the past shared resource overloaded metric of the first CPU cluster. The AMP system can assign the first thread to a different CPU cluster while other threads of the same thread group remain assigned to the first CPU cluster. The thread metric can include a Matrix Extension (MX) thread flag or a Bus Interface Unit (BIU) thread flag.

公开(公告)号：US11507381B2

公开(公告)日：2022-11-22

申请号：US17244377

申请日：2021-04-29

Applicant: Apple Inc.

Inventor： Aditya Venkataraman ,  Bryan R. Hinch ,  John G. Dorsey

IPC: G06F9/38 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/48 ,  G06F9/50

Abstract: Closed loop performance controllers of asymmetric multiprocessor systems may be configured and operated to improve performance and power efficiency of such systems by adjusting control effort parameters that determine the dynamic voltage and frequency state of the processors and coprocessors of the system in response to the workload. One example of such an arrangement includes applying hysteresis to the control effort parameter and/or seeding the control effort parameter so that the processor or coprocessor receives a returning workload in a higher performance state. Another example of such an arrangement includes deadline driven control, in which the control effort parameter for one or more processing agents may be increased in response to deadlines not being met for a workload and/or decreased in response to deadlines being met too far in advance. The performance increase/decrease may be determined by comparison of various performance metrics for each of the processing agents.

公开(公告)号：US11494193B2

公开(公告)日：2022-11-08

申请号：US17384399

申请日：2021-07-23

Applicant: Apple Inc.

Inventor： Aditya Venkataraman ,  Bryan R. Hinch ,  John G. Dorsey

IPC: G06F1/00 ,  G06F9/38 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/48 ,  G06F9/50

Abstract: Closed loop performance controllers of asymmetric multiprocessor systems may be configured and operated to improve performance and power efficiency of such systems by adjusting control effort parameters that determine the dynamic voltage and frequency state of the processors and coprocessors of the system in response to the workload. One example of such an arrangement includes applying hysteresis to the control effort parameter and/or seeding the control effort parameter so that the processor or coprocessor receives a returning workload in a higher performance state. Another example of such an arrangement includes deadline driven control, in which the control effort parameter for one or more processing agents may be increased in response to deadlines not being met for a workload and/or decreased in response to deadlines being met too far in advance. The performance increase/decrease may be determined by comparison of various performance metrics for each of the processing agents.

公开(公告)号：US11231966B2

公开(公告)日：2022-01-25

申请号：US16147077

申请日：2018-09-28

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  Daniel A. Chimene ,  Andrei Dorofeev ,  Bryan R. Hinch ,  Evan M. Hoke ,  Aditya Venkataraman

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3206 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on an asymmetric multiprocessing system having multiple core types. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Metrics for workloads offloaded to co-processors can be tracked and integrated into metrics for the offloading thread group.

公开(公告)号：US11023245B2

公开(公告)日：2021-06-01

申请号：US16376828

申请日：2019-04-05

Applicant: Apple Inc.

Inventor： Aditya Venkataraman ,  Bryan R. Hinch ,  John G. Dorsey

IPC: G06F9/38 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/48 ,  G06F9/50

Abstract: Closed loop performance controllers of asymmetric multiprocessor systems may be configured and operated to improve performance and power efficiency of such systems by adjusting control effort parameters that determine the dynamic voltage and frequency state of the processors and coprocessors of the system in response to the workload. One example of such an arrangement includes applying hysteresis to the control effort parameter and/or seeding the control effort parameter so that the processor or coprocessor receives a returning workload in a higher performance state. Another example of such an arrangement includes deadline driven control, in which the control effort parameter for one or more processing agents may be increased in response to deadlines not being met for a workload and/or decreased in response to deadlines being met too far in advance. The performance increase/decrease may be determined by comparison of various performance metrics for each of the processing agents.

公开(公告)号：US10942850B2

公开(公告)日：2021-03-09

申请号：US16513225

申请日：2019-07-16

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  Aditya Venkataraman ,  Bryan R. Hinch ,  Daniel A. Chimene ,  Andrei Dorofeev ,  Constantin Pistol

IPC: G06F12/00 ,  G06F12/0802

Abstract: A processing system can include a plurality of processing clusters. Each processing cluster can include a plurality of processor cores and a last level cache. Each processor core can include one or more dedicated caches and a plurality of counters. The plurality of counters may be configured to count different types of cache fills. The plurality of counters may be configured to count different types of cache fills, including at least one counter configured to count total cache fills and at least one counter configured to count off-cluster cache fills. Off-cluster cache fills can include at least one of cross-cluster cache fills and cache fills from system memory. The processing system can further include one or more controllers configured to control performance of one or more of the clusters, the processor cores, the fabric, and the memory responsive to cache fill metrics derived from the plurality of counters.

公开(公告)号：US10895903B2

公开(公告)日：2021-01-19

申请号：US16266248

申请日：2019-02-04

Applicant: Apple Inc.

Inventor： James S. Ismail ,  John M. Ananny ,  John G. Dorsey ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Keith Cox ,  Inder M. Sodhi ,  Achmed R. Zahir

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/20 ,  G06F1/3206 ,  G01R21/133

Abstract: In an embodiment, an electronic device includes a package power zone controller. The device monitors the overall power consumption of multiple components of a “package.” The package power zone controller may detect workloads in which the package components (e.g. different types of processors, peripheral hardware, etc.) are each consuming relatively low levels of power, but the overall power consumption is greater than a desired target. The package power zone controller may implement various mechanisms to reduce power consumption in such cases.