公开(公告)号：US11106465B2

公开(公告)日：2021-08-31

申请号：US16650999

申请日：2018-11-15

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Nigel John Stephens ,  Neil Burgess ,  Grigorios Magklis

IPC: G06F9/30 ,  G06F7/50

Abstract: Vector add-with-carry instructions are described which use some elements of a destination vector register, or corresponding fields of a predicate register, to provide the carry information corresponding to results of an add-with-carry operation. This is useful for accelerating computations involving multiplications of long integer values.

公开(公告)号：US20200257787A1

公开(公告)日：2020-08-13

申请号：US16271760

申请日：2019-02-08

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Matthew James Horsnell

IPC: G06F21/36 ,  A61B5/117 ,  A61B5/0484 ,  A61B5/00

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more processing devices to facilitate and/or support one or more operations and/or techniques for authenticating an identity of a human subject. In particular, some embodiments are directed to techniques for authentication of an identity of a human subject as being an identity of a particular unique individual based, at least in part, on involuntary responses by the human subject to sensory stimuli.

公开(公告)号：US10678506B2

公开(公告)日：2020-06-09

申请号：US15665715

申请日：2017-08-01

Applicant: ARM Limited

Inventor： Alejandro Martinez Vicente ,  Jesse Garrett Beu ,  Mbou Eyole ,  Timothy Hayes

IPC: G06F9/30 ,  G06F7/02

Abstract: An apparatus and a method of operating the apparatus are provided for performing a comparison operation to match a given sequence of values within an input vector. Instruction decoder circuitry is responsive to a string match instruction specifying a segment of an input vector to generate control signals to control the data processing circuitry to perform a comparison operation. The comparison operation determines a comparison value indicative of whether each input element of a required set of consecutive input elements of the segment has a value which matches a respective value in consecutive reference elements of the reference data item. A plurality of comparison operations may be performed to determine a match vector corresponding to the segment of the input vector to indicate the start position of the substring in the input vector. A string match instruction, as well as simulator virtual machine implementations, are also provided.

公开(公告)号：US10430192B2

公开(公告)日：2019-10-01

申请号：US15748734

申请日：2016-07-28

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  Grigorios Magklis ,  Alejandro Martinez Vicente ,  Nathanael Premillieu ,  Mbou Eyole

IPC: G06F9/30 ,  G06F9/38

Abstract: Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of a data vector comprising a plurality of data items at respective positions in the data vector, according to the state of respective predicate flags associated with the positions; the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a WHILE instruction and a CHANGE instruction, to control the instruction processing dependent upon a number of the predicate flags.

公开(公告)号：US12260221B2

公开(公告)日：2025-03-25

申请号：US18261966

申请日：2022-01-19

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Giacomo Gabrielli ,  Balaji Venu

IPC: G06F9/38

Abstract: Circuitry comprises processing circuitry configured to execute program instructions in dependence upon respective trigger conditions matching a current trigger state and to set a next trigger state in response to program instruction execution; the processing circuitry comprising: instruction storage configured to selectively provide a group of two or more program instructions for execution in parallel; and trigger circuitry responsive to the generation of a trigger state by execution of program instructions and to a trigger condition associated with a given group of program instructions, to control the instruction storage to provide program instructions of the given group of program instructions for execution.

公开(公告)号：US12061906B2

公开(公告)日：2024-08-13

申请号：US15745478

申请日：2016-06-15

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  Jacob Eapen ,  Mbou Eyole

IPC: G06F9/315 ,  G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30018 ,  G06F9/30036

Abstract: An apparatus and a method are provided for performing a splice operation, the apparatus having a set of vector registers and one or more control registers. Processing circuitry is arranged to execute a sequence of instructions including a splice instruction that identifies at least a first vector register and at least one control register. The first vector register stores a first vector of data elements having a vector length, and the at least one control register stores control data identifying one or more data elements occupying sequential data element positions within the first vector of data elements. The processing circuitry is responsive to execution of the splice instruction to extract from the first vector each data element identified by the control data in the at least one control register, and to output the extracted data elements within sequential data element positions of the result vector starting from a first end of the result vector, and data elements from a second vector are output to the remaining result vector data element positions not occupied by the extracted data elements from the first vector.

公开(公告)号：US11966739B2

公开(公告)日：2024-04-23

申请号：US17941387

申请日：2022-09-09

Applicant: Arm Limited

Inventor： Matthew James Walker ,  Mbou Eyole ,  Giacomo Gabrielli ,  Balaji Venu

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30138 ,  G06F9/3824 ,  G06F9/4881 ,  G06F9/30098 ,  G06F9/30145

Abstract: There is provided an apparatus, method and medium for data processing. The apparatus comprises a register file comprising a plurality of data registers, and frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item. The processing circuitry is responsive to a first encoding of the issued instruction specifying a data register, to read the input data item from the data register, and/or write the output data item to the data register. The processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perform the processing operation and to perform a dequeue operation to dequeue the input data item from the queue, and/or perform an enqueue operation to enqueue the output data item to the queue.

公开(公告)号：US11899940B2

公开(公告)日：2024-02-13

申请号：US17755133

申请日：2020-10-07

Applicant: ARM LIMITED

Inventor： Mbou Eyole ,  Stefanos Kaxiras

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0629 ,  G06F3/0673

Abstract: When load requests are generated to support data processing operations, the load requests are buffered in pending load buffer circuitry prior to being carried out. Coalescing circuitry determines for a first load request whether a set of one or more subsequent load requests buffered in the pending load buffer circuitry satisfies an address proximity condition. The address proximity condition is satisfied when all data items identified by the set of one or more subsequent load requests are comprised within a series of data items which will be retrieved from the memory system in response to the first load request. When the address proximity condition is satisfied, forwarding of the set of one or more subsequent load requests is suppressed.

公开(公告)号：US11847460B2

公开(公告)日：2023-12-19

申请号：US17211062

申请日：2021-03-24

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Michiel Willem Van Tol

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30043 ,  G06F9/3838

Abstract: Apparatuses and methods for handling load requests are disclosed. In response to a load request specifying a data item to retrieve from memory, a series of data items comprising the data item identified by the load request are retrieved. Load requests are buffered prior to the load requests being carried out. Coalescing circuitry determines for the load request and a set of one or more other load requests buffered in the pending load buffer circuitry whether an address proximity condition is true. The address proximity condition is true when all data items identified by the set of one or more other load requests are comprised within the series of data items. When the address proximity condition is true, the set of one or more other load requests are suppressed. Coalescing prediction circuitry generates a coalescing prediction for each load request based on previous handling of load requests by the coalescing circuitry.

公开(公告)号：US11803627B2

公开(公告)日：2023-10-31

申请号：US16271760

申请日：2019-02-08

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Matthew James Horsnell

IPC: A61B5/117 ,  G06F21/36 ,  A61B5/00 ,  A61B5/38 ,  A61B5/378

CPC classification number: G06F21/36 ,  A61B5/0053 ,  A61B5/117 ,  A61B5/378 ,  A61B5/38 ,  A61B5/7264

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more processing devices to facilitate and/or support one or more operations and/or techniques for authenticating an identity of a human subject. In particular, some embodiments are directed to techniques for authentication of an identity of a human subject as being an identity of a particular unique individual based, at least in part, on involuntary responses by the human subject to sensory stimuli.