公开(公告)号：US20210165721A1

公开(公告)日：2021-06-03

申请号：US16700993

申请日：2019-12-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Michael Ignatowski ,  Vilas Sridharan

IPC: G06F11/20

Abstract: A method includes reserving memory capacity in a first memory device as patch memory region for backing faulted memory, receiving a memory error indication indicating an uncorrectable error in a faulted segment in a second memory device and, in response to the memory error indication, associating in a remapping table the faulted segment with a patch segment in the patch memory region. The faulted segment is smaller than a memory page size of the second memory device. The method also includes, in response to receiving a memory access request directed to the faulted memory segment, servicing the memory access request from the patch segment by querying the remapping table to determine a patch segment address corresponding to a requested memory address, where the patch segment address identifies the location of the patch segment, and based on the patch segment address, performing the requested memory access at the patch segment.

公开(公告)号：US20200301849A1

公开(公告)日：2020-09-24

申请号：US16894473

申请日：2020-06-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Andrew G. Kegel

IPC: G06F12/1009 ,  G06F12/1081 ,  G06F12/1027 ,  G06F3/06

Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.

公开(公告)号：US10592279B2

公开(公告)日：2020-03-17

申请号：US15191355

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Dmitri Yudanov ,  David A. Roberts ,  Mitesh R. Meswani ,  Sergey Blagodurov

IPC: G06F9/52 ,  G06F9/48 ,  G06F11/34 ,  G06F9/50

Abstract: A method and processing apparatus for accelerating program processing is provided that includes a plurality of processors configured to process a plurality of tasks of a program and a controller. The controller is configured to determine, from the plurality of tasks being processed by the plurality of processors, a task being processed on a first processor to be a lagging task causing a delay in execution of one or more other tasks of the plurality of tasks. The controller is further configured to provide the determined lagging task to a second processor to be executed by the second processor to accelerate execution of the lagging task.

公开(公告)号：US10171382B2

公开(公告)日：2019-01-01

申请号：US14748209

申请日：2015-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov

IPC: G06F15/173 ,  H04L12/911 ,  G06F3/06 ,  H04L12/721

Abstract: A method of managing memory in a network of nodes includes identifying memory resources for each of the plurality of nodes connected to the network, storing memory resource information describing the memory resources, and based on the stored memory resource information, allocating a portion of the memory resources for execution of instructions in a workload, where at least a first node of the plurality of nodes is configured to execute the workload using the allocated portion of the memory resources.

公开(公告)号：US20180077228A1

公开(公告)日：2018-03-15

申请号：US15265402

申请日：2016-09-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov

IPC: H04L29/08 ,  H04L12/24

CPC classification number: H04L67/1008 ,  H04L41/0816 ,  H04L41/0896 ,  H04L45/30 ,  H04L47/805

Abstract: A server includes a plurality of nodes that are connected by a network that includes an on-chip network or an inter-chip network that connects the nodes. The server also includes a controller to configure the network based on relative priorities of workloads that are executing on the nodes. Configuring the network can include allocating buffers to virtual channels supported by the network based on the relative priorities of the workloads associated with the virtual channels, configuring routing tables that route the packets over the network based on the relative priorities of the workloads that generate the packets, or modifying arbitration weights to favor granting access to the virtual channels to packets generated by higher priority workloads.

公开(公告)号：US20170371720A1

公开(公告)日：2017-12-28

申请号：US15191355

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Dmitri Yudanov ,  David A. Roberts ,  Mitesh R. Meswani ,  Sergey Blagodurov

IPC: G06F9/52

Abstract: A method and processing apparatus for accelerating program processing is provided that includes a plurality of processors configured to process a plurality of tasks of a program and a controller. The controller is configured to determine, from the plurality of tasks being processed by the plurality of processors, a task being processed on a first processor to be a lagging task causing a delay in execution of one or more other tasks of the plurality of tasks. The controller is further configured to provide the determined lagging task to a second processor to be executed by the second processor to accelerate execution of the lagging task.

公开(公告)号：US20170168546A1

公开(公告)日：2017-06-15

申请号：US14963352

申请日：2015-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Mitesh R. Meswani ,  David A. Roberts ,  Dmitri Yudanov ,  Arkaprava Basu ,  Sergey Blagodurov

IPC: G06F1/32 ,  G06F1/28

CPC classification number: G06F1/3243 ,  G06F9/3885

Abstract: A method and apparatus for performing inter-lane power management includes de-energizing one or more execution lanes upon a determination that the one or more execution lanes are to be predicated. Energy from the predicated execution lanes is redistributed to one or more active execution lanes.

公开(公告)号：US20170147228A1

公开(公告)日：2017-05-25

申请号：US14952517

申请日：2015-11-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  Sergey Blagodurov ,  David A. Roberts ,  Mitesh R. Meswani ,  Nuwan Jayasena ,  Michael Ignatowski

IPC: G06F3/06

CPC classification number: G06F12/08 ,  G06F12/0811 ,  G06F12/0888 ,  G06F13/16 ,  G06F13/4022 ,  G06F15/7821 ,  G06F2212/1024

Abstract: A plurality of memory blocks are connected to a computation-enabled switch that provides data paths between the plurality of memory blocks. The computation-enabled switch performs one or more computations on data stored in one or more of the plurality of memory blocks during transfer of the data along one or more of the data paths between the plurality of memory blocks.

公开(公告)号：US20160170919A1

公开(公告)日：2016-06-16

申请号：US14569825

申请日：2014-12-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Gabriel H. Loh ,  Yasuko Eckert

IPC: G06F13/16 ,  G06F11/34 ,  G06F12/02

CPC classification number: G06F13/1694 ,  G06F11/3414 ,  G06F12/023 ,  G06F13/161 ,  G06F2212/1044 ,  Y02D10/14

Abstract: A system includes a plurality of memory classes and a set of one or more processing units coupled to the plurality of memory classes. The system further includes a data migration controller to select a traffic rate as a maximum traffic rate for transferring data between the plurality of memory classes based on a net benefit metric associated with the traffic rate, and to enforce the maximum traffic rate for transferring data between the plurality of memory classes.

Abstract translation: 系统包括多个存储器类别以及耦合到多个存储器类别的一个或多个处理单元的集合。 该系统还包括数据迁移控制器，用于基于与业务速率相关联的净利益度量来选择业务速率作为用于在多个存储器类之间传送数据的最大业务速率，并且执行用于在数据传输之间传送数据的最大业务速率 多个存储器类。

公开(公告)号：US11880312B2

公开(公告)日：2024-01-23

申请号：US17539189

申请日：2021-11-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Kishore Punniyamurthy ,  SeyedMohammad SeyedzadehDelcheh ,  Sergey Blagodurov ,  Ganesh Dasika ,  Jagadish B Kotra

IPC: G06F12/00 ,  G06F12/126 ,  G06F12/0855

CPC classification number: G06F12/126 ,  G06F12/0859 ,  G06F2212/1024 ,  G06F2212/6042

Abstract: A method includes storing a function representing a set of data elements stored in a backing memory and, in response to a first memory read request for a first data element of the set of data elements, calculating a function result representing the first data element based on the function.