公开(公告)号：US20040093601A1

公开(公告)日：2004-05-13

申请号：US10289639

申请日：2002-11-07

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  Eugene Hogenauer ,  Bicheng William Wu ,  Dan MingLun Chuang ,  Bjorn Freeman-Benson

IPC: G06F009/00

CPC classification number: G06F17/5022 ,  G06F17/5045

Abstract: A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit. The compiler generates the configuration information, from the scheduled algorithm and the selected adaptive computing circuit version, for the performance of the algorithm by the adaptive computing integrated circuit. In the exemplary embodiments, multiple versions of configuration information may be generated, for different circuit versions, different feature sets, different operating conditions, and different operating modes.

Abstract translation: 提供了一种用于开发自适应计算集成电路和相应配置信息的方法，系统和程序，其中配置信息向自适应计算集成电路提供操作模式。 示例性系统包括调度器，存储器和编译器。 调度器能够利用多个自适应计算描述对象调度所选择的算法，以产生调度算法和所选择的自适应计算电路版本。 存储器用于存储多个自适应计算描述对象和在调度过程期间生成的多个自适应计算电路版本。 所选择的自适应计算电路版本被转换成硬件描述语言，用于制造成自适应计算集成电路。 编译器从调度算法和选择的自适应计算电路版本生成配置信息，以便通过自适应计算集成电路执行算法。 在示例性实施例中，可以针对不同的电路版本，不同的特征集合，不同的操作条件和不同的操作模式来生成配置信息的多个版本。

公开(公告)号：US20040078403A1

公开(公告)日：2004-04-22

申请号：US10386896

申请日：2003-03-11

Applicant: QuickSilver Technology, Inc.

Inventor： W. James Scheuermann ,  Otis Lamont Frost III

IPC: G06F017/10

CPC classification number: H03H17/0294 ,  H03H21/0012

Abstract: A reconfigurable filter node including an input data memory adapted to store a plurality of input data values, a filter coefficient memory adapted to store a plurality of filter coefficient values, and a plurality of computational units adapted to simultaneously compute filter data values. Filter data values are the outputs of a filter in response to input data values or a second plurality of filter coefficients to be used in subsequent filter data value computations. First and second input data registers load successive input data values input data memory or from adjacent computational units. Each computational unit comprises a pre-adder adapted to output either the sum two input data values stored in the computational unit or alternately to output a single input data value, and a multiply-and-accumulate unit adapted to multiply the output of the pre-adder by a filter coefficient and accumulate the result.

Abstract translation: 一种可重构滤波器节点，包括适于存储多个输入数据值的输入数据存储器，适于存储多个滤波器系数值的滤波器系数存储器，以及适于同时计算滤波器数据值的多个计算单元。 滤波器数据值是响应于输入数据值的滤波器的输出或将在随后的滤波数据值计算中使用的第二多个滤波器系数。 第一和第二输入数据寄存器加载连续的输入数据值输入数据存储器或从相邻的计算单元加载。 每个计算单元包括预加法器，其适于输出存储在计算单元中的和两个输入数据值，或者交替地输出单个输入数据值，以及乘法和累加单元， 加法器通过滤波器系数并累加结果。

公开(公告)号：US20040054997A1

公开(公告)日：2004-03-18

申请号：US10233175

申请日：2002-08-29

Applicant: QuickSilver Technology, Inc.

Inventor： Ramana Katragadda ,  Paul Spoltore ,  Ric Howard

IPC: G06F009/00

CPC classification number: G06F9/5044

Abstract: Task definitions are used by a task scheduler and prioritizer to allocate task operations to a plurality of processing units. The task definition is an electronic record that specifies resources needed by, and other characteristics of, a task to be executed. Resources include types of processing nodes desired to execute the task, needed amount or rate of processing cycles, amount of memory capacity, number of registers, input/output ports, buffer sizes, etc. Characteristics of a task in clued maximum latency time, frequency of execution of a task, communication ports, and other characteristics. An examplary task definition language and syntax is described that uses constructs including order of attempted scheduling operations, percentage or amount of resources desired by different operations, handling of multiple executable images or modules, overlays, port aliases and other features.

Abstract translation: 任务定义由任务调度器和优先级分配器用于将任务操作分配给多个处理单元。 任务定义是指定要执行的任务所需的资源和其他特征的电子记录。 资源包括执行任务所需的处理节点的类型，所需的处理周期数量或速率，存储器容量，寄存器数量，输入/输出端口，缓冲区大小等。在最大延迟时间，频率上的任务特征 执行任务，通信端口等特性。 描述了使用包括尝试调度操作的顺序，不同操作所需的资源的百分比或数量，多个可执行映像或模块的处理，覆盖，端口别名和其他特征的构造的示例性任务定义语言和语法。

公开(公告)号：US20040030736A1

公开(公告)日：2004-02-12

申请号：US10443596

申请日：2003-05-21

Applicant: QuickSilver Technology, Inc.

Inventor： W. James Scheuermann

IPC: G06F017/14

CPC classification number: G06F15/7867

Abstract: A computational unit, or node, in an adaptable computing system is described. A preferred embodiment of the node allows the node to be adapted for use for any of ten types of functionality by using a combination of execution units with a configurable interconnection scheme. Functionality types include the following: Asymmetric FIR Filter, Symmetric FIR Filter, Complex Multiply/FIR Filter, Sum-of-absolute-differences, Bi-linear Interpolation, Biquad IIR Filter, Radix-2 FFT/IFFT, Radix-2 DCT/IDCT, Golay Correlator, Local Oscillator/Mixer.

Abstract translation: 描述了可适应性计算系统中的计算单元或节点。 节点的优选实施例允许通过使用具有可配置互连方案的执行单元的组合来适配用于十种类型的功能中的任何一种的节点。 功能类型包括：不对称FIR滤波器，对称FIR滤波器，复乘数FIR滤波器，绝对差值和双线性插值，二维IIR滤波器，二进制FFT / IFFT，二进制DCT / IDCT ，Golay相关器，本地振荡器/混频器。

公开(公告)号：US20040028082A1

公开(公告)日：2004-02-12

申请号：US10013825

申请日：2001-12-10

Applicant: Quicksilver Technology, Inc.

Inventor： Paul L. Master ,  John Watson

IPC: H04J001/02

CPC classification number: G06Q30/02

Abstract: A system for efficient sale of devices that comply with licensed standards. A preferred embodiment of the invention uses a generic, or highly adaptable, hardware device. The device can be adapted to adhere to a specific standard, e.g., code-division multiple access, time-division multiple access, etc., after manufacture such as at the point-of-sale to an end user, prior to distribution, or at some other point in a distribution and sales network. This allows manufacturers, retailers and end users to benefit from more competitive selection of standardized communication, data and other formats. Reduction of manufacturing costs and elimination of shipping, or other transfer and storage costs, is also realized.

Abstract translation: 一种高效销售符合许可标准的设备的系统。 本发明的优选实施例使用通用或高适应性的硬件设备。 该设备可以在分发之前适应于遵守特定标准，例如在诸如销售点的制造之后的码分多址，时分多路访问等到最终用户，或者 在分销和销售网络的其他一点。 这允许制造商，零售商和最终用户从更具竞争力的标准化通信，数据和其他格式的选择中受益。 降低制造成本和消除运输，或其他转运和储存成本也得以实现。

公开(公告)号：US20040010645A1

公开(公告)日：2004-01-15

申请号：US10443554

申请日：2003-05-21

Applicant: QuickSilver Technology, Inc.

Inventor： W. James Scheuermann ,  Eugene B. Hogenauer

IPC: G06F013/00

CPC classification number: G06F9/4494

Abstract: A computational unit, or node, in an adaptive computing engine uses a uniform interface to a network to communicate with other nodes and resources. The uniform interface is referred to as a nullnode wrapper.null The node wrapper includes a hardware task manager (HTM), a data distributor, optional direct memory access (DMA) engine and a data aggregator. The hardware task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The HTM coordinates a nodes assigned tasks using a task lists. A nullready-to-run queuenull is implemented as a first-in first-out stack. The HTM uses a top-level finite-state machine (FSM) that communicates with a number of subordinate FSMs to control individual HTM components. The Data Distributor interfaces between the node's input pipeline register and various memories and registers within the node. Different types of data distribution are possible based upon the values in service and auxiliary fields of a 50-bit control structure. The Data Aggregator arbitrates among up to four node elements that request access to the node's output pipeline register for the purpose of transferring data to the intended destination via the network. The DMA Engine uses a five-register model. The registers include a Starting Address Register, an Address Stride Register, a Transfer Count Register, a Duty Cycle Register, and a Control Register including a GO bit, Target Node number/port number, and DONE protocol. A control node, or nullK-node,null is used to control various aspects of the HTM, data distributor, data aggregator and DMA operations within the nodes of the system.

Abstract translation: 自适应计算引擎中的计算单元或节点使用与网络的统一接口与其他节点和资源进行通信。 统一接口被称为“节点包装器”。 节点包装器包括硬件任务管理器（HTM），数据分配器，可选的直接存储器访问（DMA）引擎和数据聚合器。 硬件任务管理器指示输入和输出缓冲区资源何时足以允许任务执行。 HTM使用任务列表协调节点分配的任务。 “即时运行队列”作为先进先出的堆栈实现。 HTM使用与许多从属FSM通信的顶级有限状态机（FSM）来控制各个HTM组件。 数据分发器在节点的输入流水线寄存器与节点内的各种存储器和寄存器之间进行接口。 基于50位控制结构的服务和辅助字段的值，可以实现不同类型的数据分发。 数据聚合器在最多四个节点元素之间进行仲裁，这些元素要求访问节点的输出流水线寄存器，以便通过网络将数据传输到预期的目的地。 DMA引擎使用五注册模型。 这些寄存器包括起始地址寄存器，地址步进寄存器，传输计数寄存器，占空比寄存器和包含GO位，目标节点号/端口号和DONE协议的控制寄存器。 控制节点或“K节点”用于控制系统节点内的HTM，数据分发器，数据聚合器和DMA操作的各个方面。

公开(公告)号：US20030204638A1

公开(公告)日：2003-10-30

申请号：US10136055

申请日：2002-04-29

Applicant: QuickSilver Technology, Inc.

Inventor： Eric Murray

IPC: G06F009/00 ,  G06F009/44

CPC classification number: G06F9/45508

Abstract: A method and apparatus for encoding/decoding between interchange format data and structured data utilizes a scripting language. The structure of the data can be controlled by the sequence of commands in the script and changes to the structure can be implemented by changing the script. A parser/interpreter is the only software necessary to implement the technique.

Abstract translation: 用于在交换格式数据和结构化数据之间进行编码/解码的方法和装置利用脚本语言。 数据的结构可以通过脚本中的命令顺序进行控制，更改结构可以通过更改脚本来实现。 解析器/解释器是实现该技术所必需的唯一软件。

公开(公告)号：US20040268096A1

公开(公告)日：2004-12-30

申请号：US10606031

申请日：2003-06-25

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  John Watson

IPC: G06F007/38 ,  G06F009/00 ,  G06F009/44 ,  G06F015/00 ,  H04N005/228

CPC classification number: G06F7/5443 ,  G06F7/4806 ,  G06F9/3001 ,  G06F9/3885 ,  G06F9/3897 ,  H03H17/0294

Abstract: The present invention provides a digital imaging apparatus having an optical sensor, an analog-to-digital converter, a plurality of computational elements, and an interconnection network. The optical sensor converts an object image into a detected image, which is then converted to digital image information by the analog-to-digital converter. The plurality of computational elements includes a first computational element having a first fixed architecture and a second computational element having a second, different fixed architecture. The interconnection network is capable of providing a processed digital image from the digital image information by configuring and reconfiguring the plurality of computational elements for performance of a plurality of different imaging functions. The invention may be embodied, for example, as a digital camera, a scanner, a printer, or a dry copier.

Abstract translation: 本发明提供一种具有光学传感器，模数转换器，多个计算元件和互连网络的数字成像设备。 光学传感器将对象图像转换为检测图像，然后通过模数转换器将其转换为数字图像信息。 多个计算元件包括具有第一固定架构的第一计算元件和具有第二不同固定架构的第二计算元件。 互连网络能够通过配置和重新配置用于执行多个不同成像功能的多个计算元件从数字图像信息提供经处理的数字图像。 本发明可以被实现为例如数字照相机，扫描仪，打印机或干式复印机。

公开(公告)号：US20040181614A1

公开(公告)日：2004-09-16

申请号：US10719409

申请日：2003-11-22

Applicant: Quicksilver Technology, Inc.

Inventor： Frederick Curtis Furtek ,  Paul L. Master ,  Robert Thomas Plunkett

IPC: G06F003/00

CPC classification number: G06F13/385 ,  G06F2213/0038

Abstract: A reconfigurable input/output controller (IOC) allows an adaptive computing engine (ACE) to communicate with external devices. The external devices can comprise a separate system on chip (SOC) or can be other devices or resources such as audio/visual output devices, memory, network or other communications, etc. The IOC allows different modes of transfer and performs necessary translation of input and output commands. In one embodiment, the IOC adheres to standard messaging and communication protocol used by other nodes in the ACE. This approach allows a uniform approach to the ACE design and provides advantages in scalability and adaptability of the ACE system. One feature of the invention provides a physical link adapter for accommodating different external communication types such as, RS231, optical, Firewire, universal synchronous bus (USB), etc. The physical link adapter uses a reconfigurable finite state machine, selectable couplings and a bus switch to allow connection of different communication types' signals to a common ACE component such as to an IOC.

Abstract translation: 可重配置输入/输出控制器（IOC）允许自适应计算引擎（ACE）与外部设备进行通信。 外部设备可以包括单独的片上系统（SOC）或者可以是诸如音频/视频输出设备，存储器，网络或其他通信之类的其他设备或资源.IOC允许不同的传输模式并执行输入的必要的转换 并输出命令。 在一个实施例中，IOC遵守ACE中其他节点使用的标准消息和通信协议。 这种方法允许对ACE设计采用统一的方法，并在ACE系统的可扩展性和适应性方面提供优势。 本发明的一个特征提供一种用于适应不同外部通信类型（例如RS231，光学，火线，通用同步总线（USB）等）的物理链路适配器。物理链路适配器使用可重构的有限状态机，可选择的耦合和总线 切换以允许将不同通信类型的信号连接到公共ACE组件，例如IOC。

公开(公告)号：US20040177225A1

公开(公告)日：2004-09-09

申请号：US10719921

申请日：2003-11-20

Applicant: QuickSilver Technology, Inc.

Inventor： Frederick Curtis Furtek ,  Paul L. Master

IPC: G06F013/00

CPC classification number: G06F15/167 ,  G06F3/0626 ,  G06F3/0661 ,  G06F3/0679 ,  G06F13/1657 ,  G11C7/1072 ,  H04L67/32

Abstract: A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.

Abstract translation: 提供了一种在自适应计算引擎中提供存储器访问服务的存储器控​​制器。 控制器包括：被配置为从可编程网络接收存储器请求的网络接口; 以及存储器接口，被配置为访问存储器以满足来自可编程网络的存储器请求，其中存储器接口接收并向网络接口提供存储器请求的数据，网络接口被配置为向可编程网络发送数据并从可编程 网络。