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公开(公告)号：US20120307141A1
公开(公告)日：2012-12-06
申请号：US13194821
申请日：2011-07-29
IPC分类号： H04N7/01
CPC分类号： G06T3/40 , G06F3/1431 , G09G5/005 , G09G5/18 , G09G2340/0414 , G09G2340/0421 , G09G2340/0442 , G09G2370/04 , H04N5/126 , H04N19/61 , H04N19/85
摘要： An inline scaling unit configured to retime an input video frame is disclosed. The scaling unit is configured to receive pixels within a line of a video frame to be displayed on a primary display that is within a first clock domain. The scaling unit down-scales the group of pixels and writes the down-scaled pixels to a buffer circuit in the first clock domain. The scaling unit includes a control circuit configured to generate horizontal and vertical control signals for the retimed video frame to be displayed on a secondary display that is within a second clock domain. The horizontal and vertical control signals are then used to enable reading from the buffer circuit in the second clock domain. The scaling unit outputs the down-scaled pixels and the generated control signals within the retimed video frame such that input video frame and the retimed video frame may be displayed concurrently.
摘要翻译： 公开了配置用于重新输入视频帧的内联缩放单元。 缩放单元被配置为接收要显示在第一时钟域内的主显示器上的视频帧的行内的像素。 缩放单元缩小像素组，并将缩小的像素写入第一时钟域中的缓冲电路。 缩放单元包括控制电路，该控制电路被配置为产生要在第二时钟域内的辅助显示器上显示的重新定时视频帧的水平和垂直控制信号。 然后，水平和垂直控制信号用于使能从第二时钟域中的缓冲电路读取。 缩放单元输出重定时视频帧内的缩小像素和生成的控制信号，使得可以同时显示输入视频帧和重新定时视频帧。
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公开(公告)号：US20120206657A1
公开(公告)日：2012-08-16
申请号：US13026557
申请日：2011-02-14
申请人： Joseph P. Bratt , Peter F. Holland
发明人： Joseph P. Bratt , Peter F. Holland
IPC分类号： H04N9/64
CPC分类号： H04N9/646 , G06F7/584 , G09G2320/0271
摘要： A display pipe unit for processing pixels of video and/or image frames may be injected with dither-noise during processing of the pixels. A random noise generator implemented using Linear Feedback Shift Registers (LFSRs) produces pseudo-random numbers that are injected into the display pipe as dither-noise. Typically, such LFSRs shift freely during operation and the values of the LFSRs are used as needed. By shifting the LFSRs when the values are used to inject noise into newly received data, and not shifting the LFSRs when no new data is received, variations in the delays of receiving the data do not affect the pattern of noise applied to the frames. Therefore, dither-noise can be deterministically injected into the display pipe during testing/debug operation. By updating the LFSRs when new pixel data is available from the host interface instead of updating the LFSRs every cycle, the same dither-noise can be injected for the same received data.
摘要翻译： 用于处理视频和/或图像帧的像素的显示管单元可以在处理像素期间被注入抖动噪声。 使用线性反馈移位寄存器（LFSR）实现的随机噪声发生器产生作为抖动噪声注入显示管道的伪随机数。 通常，这样的LFSR在操作期间自由移动，并且根据需要使用LFSR的值。 当使用这些值将噪声注入到新接收到的数据中时，通过移位LFSR，并且在没有接收到新数据时不移动LFSR，接收数据的延迟的变化不影响施加到帧的噪声模式。 因此，在测试/调试操作期间，可以将抖动噪声确定性地注入显示管道。 当从主机接口获得新像素数据而不是每个周期更新LFSR时，通过更新LFSR，可以为相同的接收数据注入相同的抖动噪声。
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公开(公告)号：US20120206468A1
公开(公告)日：2012-08-16
申请号：US13026559
申请日：2011-02-14
IPC分类号： G09G5/36
CPC分类号： G06T15/005 , G06T13/80 , G06T15/503
摘要： A video display pipe used for processing pixels of video and/or image frames may include edge Alpha registers for storing edge Alpha values corresponding to the edges of an image to be translated across a display screen. The edge Alpha values may be specified based on the fractional pixel value by which the image is to be moved in the current frame. The video pipe may copy the column and row of pixels that are in the direction of travel, and may apply the edge Alpha values to the copied column and row. The edge Alpha values may control blending of the additional column and row of the translated image with the adjacent pixels in the original frame, providing the effect of the partial pixel movement, simulating a sub-pixel rate of movement.
摘要翻译： 用于处理视频和/或图像帧的像素的视频显示管可以包括边缘Alpha寄存器，用于存储与通过显示屏幕翻译的图像的边缘相对应的边缘α值。 可以基于在当前帧中移动图像的分数像素值来指定边缘Alpha值。 视频管道可以复制行进方向的像素列和行，并且可以将边缘Alpha值应用于复制的列和行。 边缘Alpha值可以控制翻转图像的附加列和行与原始帧中的相邻像素的混合，从而提供部分像素移动的效果，模拟子像素移动速率。
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公开(公告)号：US08717391B2
公开(公告)日：2014-05-06
申请号：US12950267
申请日：2010-11-19
申请人： Joseph P. Bratt , Peter F. Holland
发明人： Joseph P. Bratt , Peter F. Holland
摘要： A display pipe may include fetch circuitry and a scaler unit, and registers programmable with information that defines active regions of an image frame. Pixels within the active regions are active pixels to be displayed, pixels outside of the active regions are inactive pixels not to be displayed. The fetch circuitry may retrieve frames from memory, retrieving the active pixels and not retrieving the inactive pixels as defined by the programmed contents of the registers. A scaler unit may produce scaled pixels from the fetched pixels, basing each scaled pixel on a respective corresponding set of pixels. When a given pixel of the respective corresponding set of pixels is an inactive pixel, the scaler unit may assign an estimated value to the given pixel based on one or more active pixels in the respective corresponding set of pixels. The scaler unit may provide the scaled pixels to a blend unit for blending with other pixels.
摘要翻译： 显示管可以包括提取电路和缩放器单元，并且可以用定义图像帧的有效区域的信息来编程。 活动区域内的像素是要显示的活动像素，活动区域之外的像素是不显示的不活动像素。 提取电路可以从存储器检索帧，检索有效像素，而不检索由寄存器的编程内容定义的非活动像素。 缩放器单元可以从获取的像素产生缩放的像素，将每个缩放的像素基于相应的相应的像素集。 当相应的相应像素集合的给定像素是非活动像素时，缩放器单元可以基于相应的相应像素集合中的一个或多个有效像素来分配给定像素的估计值。 缩放器单元可以将缩放的像素提供给用于与其他像素混合的混合单元。
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公开(公告)号：US20120206474A1
公开(公告)日：2012-08-16
申请号：US13026554
申请日：2011-02-14
申请人： Peter F. Holland , Vaughn T. Arnold
发明人： Peter F. Holland , Vaughn T. Arnold
IPC分类号： G09G5/02
CPC分类号： G09G5/377 , G09G5/026 , G09G5/397 , G09G2340/125 , G09G2352/00 , G09G2360/10 , G09G2360/121 , G09G2360/128
摘要： A blend unit in a display pipe for processing pixels of video and/or image frames may include multiple blend stages, where each blend stage may include multiple levels for blending pixels according to a blend equation. The blending operation includes blending pixel color values and Alpha values. A multiplication may be performed at each blend level, necessitating Alpha value normalizations in the form of divisions to obtain pixel color values having a specified bit-length. Color value normalizations are not needed when the desired result is an actual color value. In order to reduce the compounding of errors that may result from the introduction of an error at each division, Alpha value normalizations may not be performed at each blend level, carrying the intermediate results forward in fractional form—through one or multiple blend stages—until the end of the blending operation. At or after the final blend level—in each blend stage, or in a final blend stage—a single division may performed, preventing the compounding of errors that would be incurred at each blend level if a division at each blend level were performed.
摘要翻译： 用于处理视频和/或图像帧的像素的显示管道中的混合单元可以包括多个混合阶段，其中每个混合阶段可以包括根据混合方程来混合像素的多个级别。 混合操作包括混合像素颜色值和Alpha值。 可以在每个混合级别执行乘法，使得以分割的形式进行Alpha值归一化以获得具有指定位长的像素颜色值。 当期望的结果是实际的颜色值时，不需要颜色值归一化。 为了减少每个部门引入错误可能导致的错误复合，可能不会在每个混合级别执行Alpha值标准化，通过一个或多个混合阶段将分数形式的中间结果提前到达，直到 混合操作结束。 在最终混合水平或最终混合水平之后或在最终混合阶段，或在最后的混合阶段，可进行单一分割，防止如果进行每个共混物级别的划分，则在每个混合物水平下会发生错误的混合。
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公开(公告)号：US20120127193A1
公开(公告)日：2012-05-24
申请号：US12950267
申请日：2010-11-19
申请人： Joseph P. Bratt , Peter F. Holland
发明人： Joseph P. Bratt , Peter F. Holland
摘要： A display pipe may include fetch circuitry and a scaler unit, and registers programmable with information that defines active regions of an image frame. Pixels within the active regions are active pixels to be displayed, pixels outside of the active regions are inactive pixels not to be displayed. The fetch circuitry may retrieve frames from memory, retrieving the active pixels and not retrieving the inactive pixels as defined by the programmed contents of the registers. A scaler unit may produce scaled pixels from the fetched pixels, basing each scaled pixel on a respective corresponding set of pixels. When a given pixel of the respective corresponding set of pixels is an inactive pixel, the scaler unit may assign an estimated value to the given pixel based on one or more active pixels in the respective corresponding set of pixels. The scaler unit may provide the scaled pixels to a blend unit for blending with other pixels.
摘要翻译： 显示管可以包括提取电路和缩放器单元，并且可以用定义图像帧的有效区域的信息来编程。 活动区域内的像素是要显示的活动像素，活动区域之外的像素是不显示的不活动像素。 提取电路可以从存储器检索帧，检索有效像素，而不检索由寄存器的编程内容定义的非活动像素。 缩放器单元可以从获取的像素产生缩放的像素，将每个缩放的像素基于相应的相应的像素集。 当相应的相应像素集合的给定像素是非活动像素时，缩放器单元可以基于相应的相应像素集合中的一个或多个有效像素来分配给定像素的估计值。 缩放器单元可以将缩放的像素提供给用于与其他像素混合的混合单元。
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公开(公告)号：US20120127187A1
公开(公告)日：2012-05-24
申请号：US12950239
申请日：2010-11-19
IPC分类号： G09G5/36
CPC分类号： G09G5/397 , G09G5/36 , G09G2330/12 , G09G2340/0407 , G09G2340/06 , G09G2340/10 , G09G2340/125 , G09G2360/10 , G09G2360/125
摘要： Video display pipes may terminate with a FIFO (first-in first-out) buffer from which pixels are provided to a display controller to display the pixels on a graphics/video display. The display pipes may frequently process the pixels at a much higher rate than at which the display controller fetches the pixels from the FIFO buffer. In an error-checking only mode, the FIFO may be disabled, and an error-checking (e.g. CRC) block connected in front of the FIFO may receive the pixels processed by the display pipes as fast as the display pipes are capable of processing the pixels. Accordingly, the length of test/simulation time required to perform a test may be determined by the rate at which pixels are generated rather than the rate at which the display controller displays the pixels. It also becomes possible to perform testing/simulation in environments where a display is not supported or is not available. The results generated by the error-checking may be read and compared to an expected value to detect test pass/fail conditions.
摘要翻译： 视频显示管道可以用FIFO（先进先出）缓冲器终止，从而将像素提供给显示控制器以在图形/视频显示器上显示像素。 显示管道可以以比显示控制器从FIFO缓冲器提取像素的速率高得多的速率来频繁地处理像素。 在仅错误检查模式中，FIFO可以被禁用，并且连接在FIFO前面的错误校验（例如CRC）块可以像显示管能够处理显示管一样快地接收由显示管处理的像素 像素。 因此，执行测试所需的测试/模拟时间的长度可以由生成像素的速率而不是显示控制器显示像素的速率来确定。 在不支持显示或不可用的环境中也可以进行测试/模拟。 可以读取错误检查产生的结果并将其与期望值进行比较，以检测测试通过/失败条件。
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