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    Multi-port memory devices having clipping circuits therein that inhibit data errors during overlapping write and read operations
    22.
    发明授权
    Multi-port memory devices having clipping circuits therein that inhibit data errors during overlapping write and read operations 有权
    其中具有限幅电路的多端口存储器件在重写写入和读取操作期间阻止数据错误

    公开(公告)号：US07894296B2

    公开(公告)日：2011-02-22

    申请号：US12496976

    申请日：2009-07-02

    申请人： Chan-Ho Lee ,  Dong-Wook Seo

    发明人： Chan-Ho Lee ,  Dong-Wook Seo

    IPC分类号： G11C7/12

    CPC分类号： G11C8/16

    摘要： An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N-type MOS transistors) that are responsive to word line signals. The first and second read/write ports are electrically coupled to the first and second bit lines, respectively. A first clipping circuit is also provided. The first clipping circuit is responsive to a first write control signal. The first clipping circuit is configured to bias the first bit line with a read blocking voltage during a first “overlapping” operation to write data from the second bit line into the multi-port memory cell concurrently with reading data from the multi-port memory cell onto the first bit line.

    摘要翻译： 集成电路器件包括其中具有多端口存储器单元（例如，双端口SRAM单元）的存储器阵列。 该多端口存储单元至少包括第一和第二读/写端口，其可由响应于字线信号的相应存取晶体管（例如，N型MOS晶体管）提供。 第一和第二读/写端口分别电耦合到第一和第二位线。 还提供了第一限幅电路。 第一限幅电路响应于第一写入控制信号。 第一限幅电路被配置为在第一“重叠”操作期间以读取阻断电压偏置第一位线，以将来自第二位线的数据从多端口存储器单元读取数据同时写入多端口存储器单元 到第一个位线。

    BARREL MODULE AND IMAGING APPARATUS INCLUDING THE SAME
    24.
    发明申请
    BARREL MODULE AND IMAGING APPARATUS INCLUDING THE SAME 有权
    BARREL模块和成像装置，包括它们

    公开(公告)号：US20100226024A1

    公开(公告)日：2010-09-09

    申请号：US12716460

    申请日：2010-03-03

    申请人： Chan-ho Lee ,  Young-eun Kim

    发明人： Chan-ho Lee ,  Young-eun Kim

    IPC分类号： G02B7/04

    CPC分类号： G03B13/32 ,  G03B3/10

    摘要： A barrel module and an imaging apparatus including the same. The barrel module includes: a base having a surface on which an image pickup device is disposed; a lens barrel disposed on the base; a driver for providing driving power to move the lens barrel up and down over the base; a clip connected to the driver to be disposed between the driver and the lens barrel; and an elastic member for providing elasticity between the lens barrel and the clip, wherein the lens barrel moves from an original position toward the base according to an external force is applied, and when the external force is removed, the lens barrel goes back to the original location due to the elasticity of the elastic member.

    摘要翻译： 枪管模块和包括其的成像装置。 枪管模块包括：具有其上设置有摄像装置的表面的基座; 设置在基座上的镜筒; 用于提供驱动力以使透镜筒在基座上上下移动的驱动器; 连接到驾驶员的夹子以设置在驾驶员和镜筒之间; 以及用于在镜筒和夹子之间提供弹性的弹性构件，其中透镜筒根据外力从原始位置朝向基座移动，并且当外力被移除时，镜筒回到 原始位置由于弹性构件的弹性。

    Power gating circuit, system on chip circuit including the same and power gating method
    25.
    发明授权
    Power gating circuit, system on chip circuit including the same and power gating method 有权
    电源门控电路，片上电路包括相同的电源门控方式

    公开(公告)号：US07782701B2

    公开(公告)日：2010-08-24

    申请号：US11846677

    申请日：2007-08-29

    申请人： Dong-Wook Seo ,  Jong-Hoon Jung ,  In-Gyu Park ,  Chan-Ho Lee

    发明人： Dong-Wook Seo ,  Jong-Hoon Jung ,  In-Gyu Park ,  Chan-Ho Lee

    IPC分类号： G11C5/14

    CPC分类号： G11C5/14 ,  H03K19/0016

    摘要： A power gating circuit of a memory device includes a power gating unit and a control unit. The power gating unit includes first, second, and third power gating transistors connected in parallel between a power supply voltage and an internal power supply voltage bus of the memory device. The three power gating transistors are sequentially turned ON. The second and third power gating transistors turn ON sequentially in response to the increasing voltage level of the bus. The timing points when the second and third power gating transistors are sequentially turned ON is based upon detecting the gradually increasing the voltage level of the internal power supply voltage. The size of the first power gating transistor may be smaller than the size of the second power gating transistor, and the size of the second power gating transistor may be smaller than the size of the third power gating transistor.

    摘要翻译： 存储器件的电源门控电路包括电源门控单元和控制单元。 电源门控单元包括并联连接在存储器件的电源电压和内部电源电压总线之间的第一，第二和第三电源门控晶体管。 三个电源门控晶体管依次导通。 第二和第三电源门控晶体管响应于总线的电压增加而依次接通。 当第二和第三功率选通晶体管依次导通时的定时点是基于检测到逐渐增加内部电源电压的电压电平。 第一功率门控晶体管的尺寸可以小于第二功率门控晶体管的尺寸，并且第二功率门控晶体管的尺寸可以小于第三功率门控晶体管的尺寸。