公开(公告)号：US20240186831A1

公开(公告)日：2024-06-06

申请号：US18494505

申请日：2023-10-25

Applicant: GAN SYSTEMS INC.

Inventor： Tiefeng SHI ,  Paul WIENER

IPC: H02J50/12 ,  H01F38/14

CPC classification number: H02J50/12 ,  H01F38/14

Abstract: High efficiency resonator coils for large gap resonant wireless power transfer (WPT), and a coil design methodology are disclosed. Resonator coils comprise a coil topology defined by coil parameters in which turn dimensions, such as trace widths and spacings of each turn, are configured to reduce or minimize a variance of the z component of magnetic field, over an area of a charging plane at a specified distance, or distance range, from the coil. A Tx resonator coil comprises a capacitor arrangement of tuning and network-matching capacitors for improved coil-to-coil efficiency and end-to-end WPT system performance, e.g. for applications such as through-wall WPT, in the range of tens of watts to at least hundreds of watts. Planar resonator coil topologies are compatible with fabrication using low cost PCB technology, e.g. with multi-layer metal, to reduce losses and improve thermal performance.

公开(公告)号：US20230111992A1

公开(公告)日：2023-04-13

申请号：US17497233

申请日：2021-10-08

Applicant: GaN Systems Inc.

Inventor： Xuechao LIU ,  Di CHEN ,  Yajie QIU

IPC: H02M1/42 ,  H02M3/335

Abstract: An AC/DC Switching Mode Power Supply (SMPS) comprises a PFC stage, an isolated LLC DC/DC converter stage, and a control circuit that provides feedback/control signals to PFC and LLC controllers, to enable a plurality of operating modes, dependent on a sensed peak AC input voltage and required output voltage Vo. The PFC provides a first DC bus voltage Vdc (e.g. 200V) for low line AC input and a second DC bus voltage (e.g. 400V) for high line or universal AC input. A multi-mode LLC converter is operable in a half-bridge mode or a full-bridge mode. For low line AC input, output voltage Vo, and PFC output Vdc, the LLC operates in full-bridge mode; for high line input, output voltage Vo and PFC output 2×Vdc, the LLC operates in half-bridge mode; for universal AC input, output voltage 2×Vo, and PFC output 2×Vdc, the LLC operates in full-bridge mode.

公开(公告)号：US20230080636A1

公开(公告)日：2023-03-16

申请号：US17881096

申请日：2022-08-04

Applicant: GaN Systems Inc.

Inventor： Thomas MACELWEE

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/20 ,  H01L29/417

Abstract: A semiconductor device structure for a power transistor structure wherein a drain terminal structure comprises field plates to control and reduce the peak intensity of the channel electric field at the drain terminal. By forming multiple field plates with the existing metallization layers, the generation of hot carriers and impact ionization near the drain can be reduced. For example, in a GaN HEMT, this effect is achieved with two field plates that have different capacitive coupling and overlap with the drain ohmic contact to achieve a reduction in the channel electric field. The use of this drain terminal structure may offer a reduction in increase of Rdson with aging that may be observed in devices after high voltage stress.

公开(公告)号：US20220416069A1

公开(公告)日：2022-12-29

申请号：US17358349

申请日：2021-06-25

Applicant: GaN Systems Inc.

Inventor： Cameron MCKNIGHT-MACNEIL ,  Ahmad MIZAN ,  Maryam ABOUIE

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L23/00

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in package body comprising dielectric layers and electrically conductive layers, and where an external dielectric coating, such as a solder resist coating is provided on one or both external sides of the package body. The solder resist coating is patterned to avoid inside corners, e.g. the solder resist does not extend around or between electrical contact areas and thermal pads. It is observed that in conventional solder resist coatings, during thermal cycling, cracks tend to initiate at high stress points, such as at sharp inside corners. A solder resist layout which omits inside corners, and comprises outside corners only, is demonstrated to provide significantly improved resistance to initiation and propagation of cracks. Where inside corners are unavoidable, they are appropriately radiused to reduce stress.

公开(公告)号：US20220360259A1

公开(公告)日：2022-11-10

申请号：US17308423

申请日：2021-05-05

Applicant: GaN Systems Inc.

Inventor： Ruoyu HOU ,  Juncheng LU ,  Larry SPAZIANI

IPC: H03K17/0812 ,  H03K17/16

Abstract: An active gate voltage control circuit for a gate driver of a power semiconductor switching device comprising a power semiconductor transistor, such as a GaN HEMT, provides active gate voltage control comprising current burst mode operation and protection mode operation. The gate-source turn-on voltage Vgs(on) is increased in burst mode operation, to allow for a temporary increase of saturation current. In protection mode operation, a multi-stage turn-off may be implemented, comprising reducing Vgs(on) to implement fast soft turn-off, followed by full turn-off to bring Vgs(on) below threshold voltage, to reduce switching transients such as Vds spikes. Circuits of example embodiments provide for burst mode operation for enhanced saturation current, to increase robustness of enhancement mode GaN power switching devices, e.g. under overcurrent and short circuit conditions, or to provide active gate voltage control which adjusts dynamically to specific operating conditions or events.

公开(公告)号：US11431261B2

公开(公告)日：2022-08-30

申请号：US17230390

申请日：2021-04-14

Applicant: GaN Systems Inc.

Inventor： Yajie Qiu ,  Xuechao Liu

IPC: H02M1/36 ,  H02M7/217 ,  H02M1/00 ,  H02J7/02

Abstract: A bulk capacitor circuit for an AC input AC/DC Switching Mode Power Supply, such as an AC/DC adapter/charger without active power factor correction, is provided, comprising a plurality of bulk capacitors having different voltage ratings, and driver and control circuitry comprising AC input voltage sensing and comparator circuitry, which enables selective connection of one or more of the plurality of bulk capacitors, responsive to a sensed AC input voltage range. A startup circuit provides power to the driver circuit initially, so that the AC input voltage can be determined before power-up and enabling of the DC/DC converter. This solution provides for a reduction in capacitor volume, with associated improvement in the power density of an isolated AC/DC power supply, while the startup circuit ensures that an appropriate bulk capacitance is connected at startup for low line AC input, to maintain the ripple voltage in an appropriate range for reliable operation.

公开(公告)号：US20220246503A1

公开(公告)日：2022-08-04

申请号：US17728220

申请日：2022-04-25

Applicant: GaN Systems Inc.

Inventor： Cameron MCKNIGHT-MACNEIL ,  Greg P. KLOWAK

IPC: H01L23/495 ,  H01L23/482 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L29/20 ,  H01L29/778 ,  H01L23/00 ,  H01L23/31

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. A dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, forms an external surface of the package covering underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability.

公开(公告)号：US20210020573A1

公开(公告)日：2021-01-21

申请号：US17061839

申请日：2020-10-02

Applicant: GaN Systems Inc.

Inventor： Thomas MACELWEE

IPC: H01L23/532 ,  H01L29/20 ,  H01L29/778

Abstract: Embedded packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a semiconductor die is embedded in a dielectric body comprising a dielectric polymer composition characterized by a conductivity transition temperature Tc, a first activation energy EaLow for conduction in a temperature range below Tc, and a second activation energy EaHigh for conduction in a temperature range above Tc. A test methodology is disclosed for selecting a dielectric epoxy composition having values of Tc, EaLow, and EaHigh that provide a conduction value below a required reliability threshold, e.g. ≤5×10−13 S/cm, for a specified operating voltage and temperature. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body is formed from a laminated dielectric epoxy composition for operation at >150 C, wherein Tc is ≥75 C, EaLow is ≤0.2 eV and EaHigh is ≤1 eV, for improved reliability for high voltage, high temperature operation.

公开(公告)号：US10290623B2

公开(公告)日：2019-05-14

申请号：US15131309

申请日：2016-04-18

Applicant: GaN Systems Inc.

Inventor： John Roberts ,  Hugues Lafontaine

IPC: H01L27/02

Abstract: An integrated gate protection device P for a GaN power transistor D1 provides negative ESD spike protection. Protection device P comprises a smaller gate width wg enhancement mode GaN transistor Pm. The source of Pm is connected to its gate, the drain of Pm is connected to the gate input of D1, and the source of Pm is connected to the intrinsic source of D1. When the gate input voltage is taken negative below the threshold voltage for reverse conduction, Pm conducts and quenches negative voltage spikes. When device P comprises a plurality of GaN protection transistors P1 to Pn, connected in series, it turns on when the gate input voltage applied to the drain of P1 goes negative by more than the sum of the threshold voltages of P1 to Pn. The combined gate width of P1 to Pn is selected to limit the gate voltage excursion of D1.

公开(公告)号：US10283501B2

公开(公告)日：2019-05-07

申请号：US15447200

申请日：2017-03-02

Applicant: GaN Systems Inc.

Inventor： Thomas Macelwee ,  Greg P. Klowak ,  Howard Tweddle

IPC: H01L29/778 ,  H01L21/78 ,  H01L21/304 ,  H01L27/088 ,  H01L29/20 ,  H01L23/528 ,  H01L23/31 ,  H01L23/58 ,  H01L21/02

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.