公开(公告)号：US20180240399A1

公开(公告)日：2018-08-23

申请号：US15900809

申请日：2018-02-21

Applicant: Novatek Microelectronics Corp.

Inventor： Kun-Yueh Lin ,  Hui-Hung Chang ,  Chien-Yu Chen

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0216 ,  G09G2310/06 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/045 ,  G09G2340/16

Abstract: A driving apparatus of a light emitting diode (LED) display device is provided. The driving apparatus includes a timing control circuit. The timing control circuit outputs a plurality of driving control signals to a gate driving circuit on an LED display panel of the LED display device. Wherein, the plurality of driving control signals includes a first driving control signal and a second driving control signal, and the pulse width of the first driving control signal in a first horizontal line period is different from the pulse width of a second driving control signal in a second horizontal line period preceding to the first horizontal line period.

公开(公告)号：US10057596B2

公开(公告)日：2018-08-21

申请号：US15345470

申请日：2016-11-07

Applicant: NOVATEK Microelectronics Corp.

Inventor： Hsiao-En Chang ,  Cheng-Wei Chou

IPC: H04N19/00 ,  H04N19/527 ,  H04N19/513 ,  H04N19/543

CPC classification number: H04N19/527 ,  H04N19/521 ,  H04N19/543

Abstract: A motion estimation method for blocks of a periodic pattern is provided, which includes determining a global motion vector corresponding to a region according to motion vectors of periodic blocks in the region; generating candidate motion vectors of a target periodic block to be encoded in a second frame; for each candidate motion vector, determining a penalty value based on at least one difference between the candidate motion vector and at least one global motion vector corresponding to at least a relative region in the first frame; for each candidate motion vector, calculating a weighted similarity value based on an original similarity value between the target periodic block of the second frame and a reference block corresponding to the candidate motion vector of the first frame, and the penalty value; and determining a motion vector of the target periodic block according to weighted similarity values of the candidate motion vectors.

公开(公告)号：US20180233102A1

公开(公告)日：2018-08-16

申请号：US15954609

申请日：2018-04-17

Applicant: Novatek Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng

IPC: G09G3/36

CPC classification number: G09G3/3685 ,  G02F1/136286 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2320/02 ,  G09G2320/0223

Abstract: A display panel including a plurality of pixel units, a plurality of source lines, a plurality of gate lines and a plurality of common electrode lines is provided. The pixels units are arranged in array. The array includes a plurality of columns and a plurality of rows. The source lines are respectively coupled with the pixel units disposed in a same column of the columns. The gate lines are respectively coupled with the pixel units disposed in a same row of the rows. The common electrode lines and gate lines extend parallelly with each other. At least one of the source date lines, the gate lines and the common electrode lines has the line widths varied along the extension direction thereof.

公开(公告)号：US10049606B2

公开(公告)日：2018-08-14

申请号：US14842844

申请日：2015-09-02

Applicant: Novatek Microelectronics Corp.

Inventor： Ting-Chun Lin ,  Shu-Wei Chang ,  Chiu-Hung Cheng ,  Chih-Kai Yu

IPC: G09G3/20

Abstract: A gate driver and a method for adjusting output channels thereof are provided. The method includes: setting a target number of the output channels; dividing the output channels into a first channel chain and a second channel chain; enabling a scanning operation of the first channel chain according to a clock signal and counting the clock signal to obtain a counting value; and when the counting value reaching a threshold value, enabling a scanning operation of the second channel chain, wherein the threshold value is determined according to a difference value between the target number and the physical number.

公开(公告)号：US10043737B2

公开(公告)日：2018-08-07

申请号：US15336821

申请日：2016-10-28

Applicant: Novatek Microelectronics Corp.

Inventor： Wen-Ching Huang ,  Tai-Hung Lin

IPC: H01L23/29 ,  H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A chip on film package includes a base film, a chip and a heat-dissipation sheet. The base film includes a first surface. The chip is disposed on the first surface and having a chip length along a first axis of the chip. The heat-dissipation sheet includes a covering portion and a first extending portion connected to the covering portion and attached to first surface. The covering portion at least partially covers the chip and having a first length along the first axis. The first extending portion has a second length along the first axis substantially longer than the first length of the covering portion, and the covering portion exposes a side surface of the chip, wherein the side surface connects a top surface and a bottom surface of the chip.

公开(公告)号：US20180213228A1

公开(公告)日：2018-07-26

申请号：US15432938

申请日：2017-02-15

Applicant: Novatek Microelectronics Corp.

Inventor： Xiaoming Bu ,  Jian-Wen Chen ,  Po-Chin Hu

IPC: H04N19/124 ,  H04N11/04 ,  H04N19/513 ,  H04N19/132 ,  H04N19/174 ,  H04N19/164 ,  H04N19/182

CPC classification number: H04N19/124 ,  H04N11/046 ,  H04N19/15 ,  H04N19/182

Abstract: The disclosure proposes a method of fixed-rate line-based embedded video compression and an image processing apparatus using the same method. The method includes at least the following steps. A current encoding frame is received. Pixels in a current encoding frame are grouped on a line-by-line basis, and the grouped pixels are packed into pixel segments. Complexity information of a current pixel segment is calculated according to the pixels therein and neighboring pixels thereof. The current pixel segment is respectively encoded in a differential pulse-coding modulation (DPCM) mode and a truncation mode to generate a DPCM bitstream and a truncated bitstream according to a quantization parameter (QP). Either the DPCM bitstream or the truncated bitstream is selected and outputted according to the complexity information. An amount of bits used by the current pixel segment is feedback to calculate a new QP corresponding to a next pixel segment to be processed.

公开(公告)号：US20180204498A1

公开(公告)日：2018-07-19

申请号：US15408426

申请日：2017-01-18

Applicant: Novatek Microelectronics Corp.

Inventor： Hsueh-Yen Yang ,  Hua-Gang Chang ,  Chun-Chieh Lin

IPC: G09G3/20

CPC classification number: G09G3/2003 ,  G06F1/1652 ,  G06F1/1677 ,  G06T5/002 ,  G06T2207/20024 ,  G09G3/3208 ,  G09G5/10 ,  G09G2320/045 ,  G09G2320/0626 ,  G09G2320/0666

Abstract: An image processing method and a display device thereof are provided. The method is adapted to a display panel with a display area. The image processing method includes the following steps. Whether original images to be displayed on a plurality of sub-areas of the display area are still is analyzed and determined. When the original image in a current sub-area is still, a time length of the original image being still is recorded. The current sub-area is one of the sub-areas. Processing levels corresponding to a plurality of image processing schemes are determined based on the time length. Overall or partial luminance (luma) of the original image in the current sub-area is gradually reduced by the image processing schemes with the determined processing levels, and a corresponding luma-reduced image is displayed on the current sub-area.

公开(公告)号：US10027280B1

公开(公告)日：2018-07-17

申请号：US15653519

申请日：2017-07-18

Applicant: Novatek Microelectronics Corp.

Inventor： Cheng-Dao Su ,  Chih-Hung Chen ,  Tzu-Cheng Yang ,  Yi-Ming Wu

IPC: H03K5/14 ,  H03B5/12 ,  H03K23/40 ,  H03K21/10 ,  H04B17/10

Abstract: An inductor-less local oscillator (LO) signal generation apparatus configured to generate one or more output signals which reduce a frequency pulling effect. The LO signal generation apparatus includes a multi-phase signal generation circuit, a phase signal generation circuit and one or more output circuits. The multi-phase signal generation circuit receives an input clock signal having a first frequency to generate a multi-phase clock signal. The multi-phase clock signal includes a plurality of clock signals each having the first frequency and different phases. The phase signal generation circuit is coupled to the multi-phase signal generation circuit to receive the multi-phase clock signal and output a plurality of phase signals indicating the phases of the clock signals. The one or more output circuits output the one or more output signals according to the clock signals and the phase signals without receiving feedback of any of the one or more output signals.

公开(公告)号：US20180158422A1

公开(公告)日：2018-06-07

申请号：US15884398

申请日：2018-01-31

Applicant: Novatek Microelectronics Corp.

Inventor： Ching-Wen Hou ,  Shun-Hsun Yang ,  Tse-Hung Wu

IPC: G09G3/36

CPC classification number: G09G3/36 ,  G09G2310/0264

Abstract: A liquid crystal display apparatus, a source driver, and a method for controlling polarity of driving signals thereof are provided. The source driver includes a signal receiving interface, a decoder, and a controller. The signal receiving interface receives an image data stream or an indication signal. The decoder obtains controlling information from the image data stream or the indication signal. The controller receives the controlling information and decides a plurality of source driving signals generated by the source driver according to the controlling information.

公开(公告)号：US09972271B2

公开(公告)日：2018-05-15

申请号：US15152575

申请日：2016-05-12

Applicant: Novatek Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng

IPC: G09G3/36

CPC classification number: G09G3/3685 ,  G02F1/13 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2320/02 ,  G09G2320/0223

Abstract: A display panel including a plurality of pixel units, a plurality of source lines, a plurality of gate lines and a plurality of common electrode lines is provided. The pixels units are arranged in array. The array includes a plurality of columns and a plurality of rows. The source lines are respectively coupled with the pixel units disposed in a same column of the columns. The gate lines are respectively coupled with the pixel units disposed in a same row of the rows. The common electrode lines and gate lines extend parallelly with each other. At least one of the source date lines, the gate lines and the common electrode lines has the line widths varied along the extension direction thereof.