公开(公告)号：US20060092984A1

公开(公告)日：2006-05-04

申请号：US11303409

申请日：2005-12-16

Applicant: Sridhar Jonnalagadda

Inventor： Sridhar Jonnalagadda

IPC: H04J3/06

CPC classification number: H04J3/0691 ,  H04J2203/0025

Abstract: Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g., pulses) are generated periodically and the timing of channels is adjusted. In an embodiment, multiple sequences of parallel data elements are received on corresponding parallel data channels using a first common clock signal. Each sequence of parallel data elements is converted to a corresponding sequence of serial data elements. The serial data elements are transmitted on a corresponding serial channel using a serial clock as a common reference. A synchronization signal may be generated periodically with a time period of (the number of bits in each parallel data element x the time period of the serial clock), wherein ‘x’ represents multiplication operation. As the parallel data channels are synchronized in short intervals, synchronization is maintained.

Abstract translation: 当使用相应的公共参考时钟信号发送/接收多个数据通道时，保持同步。 周期性地产生同步信号（例如，脉冲），并调整通道的定时。 在一个实施例中，使用第一公共时钟信号在对应的并行数据信道上接收多个并行数据元素序列。 每个并行数据元素序列被转换成相应的串行数据元素序列。 使用串行时钟作为公共参考，在相应的串行通道上发送串行数据元素。 可以周期性（每个并行数据元素x中的位数为串行时钟的时间周期）周期性地生成同步信号，其中“x”表示乘法运算。 由于并行数据信道在短时间间隔内同步，因此保持同步。

公开(公告)号：US07012917B2

公开(公告)日：2006-03-14

申请号：US10100208

申请日：2002-03-18

Applicant: Stephen J. Brolin ,  Robert W. DeMarco

Inventor： Stephen J. Brolin ,  Robert W. DeMarco

IPC: H04L12/44 ,  H04L12/46 ,  H04L12/66

CPC classification number: H04L49/557 ,  H04J3/0688 ,  H04J3/0691 ,  H04J2203/0012 ,  H04J2203/0017 ,  H04J2203/0021 ,  H04J2203/0025 ,  H04J2203/006 ,  H04L12/5601 ,  H04L49/1523 ,  H04L49/153 ,  H04L49/1553 ,  H04L49/25 ,  H04L49/30 ,  H04L49/3081 ,  H04L49/40 ,  H04L49/552 ,  H04L49/606 ,  H04L2012/5605 ,  H04L2012/5618 ,  H04L2012/5627 ,  H04L2012/5665 ,  H04Q11/0478

Abstract: Architecture for a SONET network element. The architecture includes an interconnection system for a network element, including a line unit slot, a switch fabric slot, and service unit slots. The line unit slot is connected as a hub to the switch fabric slot and the service unit slots in a first star interconnection configuration. The switch fabric slot is connected as a hub to the line unit slot and the service unit slots in a second star interconnection configuration. The star interconnection configurations provide fault isolation between different units, and allow for replacement of failed units without interfering with the links of other units to the hub. A service unit is provided including a first backplane interface for connecting with an ATM star interconnect configuration within the network element, and a second backplane interface for connecting to an STM star interconnect configuration within the network element.

Abstract translation: SONET网元的体系结构。 该架构包括用于网络元件的互连系统，包括线路单元插槽，交换矩阵插槽和服务单元插槽。 线路单元插槽作为集线器连接到交换矩阵槽，并且服务单元以第一星形互连配置插槽。 交换矩阵槽作为集线器连接到线路单元插槽，并且服务单元以第二星形互连配置插槽。 星形互连配置提供不同单元之间的故障隔离，并允许更换故障单元，而不会干扰其他单元到集线器的链路。 提供一种服务单元，包括用于与网络元件内的ATM星形互连配置连接的第一背板接口和用于连接到网络元件内的STM星形互连配置的第二背板接口。

公开(公告)号：US06944190B1

公开(公告)日：2005-09-13

申请号：US09660837

申请日：2000-09-14

Applicant: Sunil Tomar ,  Arvind Bhaskar Patwardhan ,  Srinivasarao Neelamraju

Inventor： Sunil Tomar ,  Arvind Bhaskar Patwardhan ,  Srinivasarao Neelamraju

IPC: H04J3/06 ,  H04J3/16 ,  H04Q11/04 ,  H04J3/04

CPC classification number: H04J3/1611 ,  H04J3/0688 ,  H04J2203/0007 ,  H04J2203/0008 ,  H04J2203/0025 ,  H04J2203/0026

Abstract: A plurality of transmission circuits transmit data over one or more output lines. A plurality of receiving circuits receive data over one or more of a set of input lines A plurality of parallel-serial conversion circuits coupled to the plurality of transmission circuits and to the plurality of receiving circuits, the plurality of conversion circuits to convert parallel signals to one or more sets of serial signals and to send the converted serial signals to one or more corresponding transmission circuits, and to receive one or more sets of serial signals from one or more of the receiving circuits and to convert the serial signals to parallel signals.

Abstract translation: 多个发送电路通过一条或多条输出线路发送数据。 多个接收电路通过一组输入线路中的一个或多个接收数据，多个并行 - 串行转换电路耦合到多个发送电路和多个接收电路，多个转换电路将并行信号转换为 一组或多组串行信号，并将转换的串行信号发送到一个或多个对应的传输电路，并从一个或多个接收电路接收一组或多组串行信号，并将串行信号转换成并行信号。

公开(公告)号：US06795393B1

公开(公告)日：2004-09-21

申请号：US09690153

申请日：2000-10-16

Applicant: Anthony Mazzurco ,  Joseph A. Crossett, III ,  Jie Hu

Inventor： Anthony Mazzurco ,  Joseph A. Crossett, III ,  Jie Hu

IPC: G01R3108

CPC classification number: H04Q3/68 ,  H04J3/0685 ,  H04J3/14 ,  H04J2203/0012 ,  H04J2203/0025 ,  H04J2203/006 ,  H04J2203/0089 ,  H04Q2213/13003 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13167

Abstract: An apparatus and a method for cross connect matrices includes originating, center and terminating stages in both a main portion and a back-up portion that allows center stages to be switched without causing a framing error. The signal from the main portion is transmitted through both the back-up and main portions of the cross connect matrices such that a terminating line card receives a frame aligned signal from the main and back portions. The terminating line card then switches its output to be the signal produced by the back-up portion with no framing error. In the main portion, the center stage may be switched. After the center stage is switched, the terminating line card can switch again to output the signal from the main portion.

Abstract translation: 用于交叉连接矩阵的装置和方法包括允许中心级被切换而不引起帧错误的主部分和备用部分中的起始，中心和终止级。 来自主要部分的信号通过交叉连接矩阵的备份和主要部分传输，使得终端线卡接收来自主要部分和后部的帧对准信号。 然后，终端线路卡将其输出切换为由备份部分产生的信号，而不产生帧错误。 在主要部分，可以切换中心台。 中间级切换后，终端线卡可以重新切换，从主部分输出信号。

公开(公告)号：US06781984B1

公开(公告)日：2004-08-24

申请号：US09698834

申请日：2000-10-27

Applicant: Joel F. Adam ,  Darren Engelkemier

Inventor： Joel F. Adam ,  Darren Engelkemier

IPC: H04J306

CPC classification number: H04L47/29 ,  H04J3/062 ,  H04J2203/0025

Abstract: Consistent with the present invention, programmable input and output buffers are provided on each port of each stage of a distributed system in order to reduce data skew and preserve data synchronization. The programmable buffers provide the ability to add delay to data paths having less skew to compensate or match the skew associated with data paths having greater skew. Accordingly, the programmable buffers can equalize data skew and preserve data synchronization at each stage in the distributed system. As a result, individual stages can be placed farther apart, thereby facilitating larger distributed systems.

Abstract translation: 根据本发明，在分布式系统的每个级的每个端口上提供可编程输入和输出缓冲器，以便减少数据偏移并保持数据同步。 可编程缓冲器提供对具有较少偏斜的数据路径添加延迟以补偿或匹配与具有较大偏斜的数据路径相关联的偏斜的能力。 因此，可编程缓冲器可以均衡数据偏移并保持分布式系统中每个阶段的数据同步。 因此，各个阶段可以放置得更远，从而便于更大的分布式系统。

公开(公告)号：US06731628B1

公开(公告)日：2004-05-04

申请号：US09257269

申请日：1999-02-25

Applicant: Kohei Shiomoto ,  Naoaki Yamanaka

Inventor： Kohei Shiomoto ,  Naoaki Yamanaka

IPC: H04L1266

CPC classification number: H04Q11/0478 ,  H04J2203/0025 ,  H04J2203/0046 ,  H04J2203/0053 ,  H04J2203/0066 ,  H04J2203/0083

Abstract: A local switch serving a terminal constituting the destination of an IP packet is identified from the IP address of the packet, and time slot switching information is formed, this being information relating to a route through an STM network to this local switch. The packet can then be transferred through the STM network in accordance with this time slot switching information. As a result, a packet with an IP address can be transferred through an STM network.

Abstract translation: 从分组的IP地址识别服务于构成IP分组的目的地的终端的本地交换机，形成时隙切换信息，这是与通过STM网络到本地交换机的路由有关的信息。 然后可以根据该时隙切换信息通过STM网络传送分组。 因此，具有IP地址的分组可以通过STM网络传输。

公开(公告)号：US20040008708A1

公开(公告)日：2004-01-15

申请号：US10193579

申请日：2002-07-11

Inventor： Peter J. Giacomini

IPC: H04L012/56 ,  H04J003/02

CPC classification number: H04J3/1611 ,  H04J2203/0021 ,  H04J2203/0025

Abstract: A novel overhead engine for processing overhead blocks (e.g., SONET/SDH overhead rows of 3 bytes, etc.) in a telecommunications node is disclosed. Some embodiments of the present invention advantageously employ a single instance of logic to process overhead blocks for all of a node's input ports. The illustrative embodiment comprises a plurality of multiport cell processors for generating output overhead cells based on input overhead cells, a dispatcher for dispatching input overhead cells to the multiport cell processors, a plurality of aggregators for combining output overhead cells into output overhead blocks, and a scheduler for controlling the order in which output overhead blocks are sent to output processors associated with a node's output ports.

Abstract translation: 公开了一种用于处理电信节点中的开销块（例如，3字节的SONET / SDH开销行等）的新型开销引擎。 本发明的一些实施例有利地采用单个逻辑实例来处理节点的所有输入端口的开销块。 说明性实施例包括多个多端口单元处理器，用于基于输入开销单元生成输出开销单元，用于将输入开销单元分配到多端口单元处理器的调度器，用于将输出开销单元组合成输出开销块的多个聚合器，以及 用于控制将输出开销块发送到与节点的输出端口相关联的输出处理器的顺序的调度器。

公开(公告)号：US06665265B1

公开(公告)日：2003-12-16

申请号：US09435749

申请日：1999-11-08

Applicant: S. Babar Raza

Inventor： S. Babar Raza

IPC: H04L106

CPC classification number: H04J3/04 ,  H04J3/14 ,  H04J2203/0025 ,  H04J2203/006 ,  H04L1/00

Abstract: A method of validating data between a path generator and a path processor, comprising the steps of (A) transmitting validation data from said path generator to said path processor on a data path, (B) sequentially transmitting data on said data path, (C) determining if the transmitted data is valid in response to the validation data and (D) using the overhead data by the processor when the overhead data is validated by the validation data.

Abstract translation: 一种验证路径生成器和路径处理器之间的数据的方法，包括以下步骤：（A）在数据路径上从所述路径生成器向所述路径处理器发送验证数据，（B）在所述数据路径上顺序发送数据，（C ）确定所发送的数据是否响应于验证数据是有效的，并且（D）当开销数据由验证数据验证时，由处理器使用开销数据。

公开(公告)号：US06587470B1

公开(公告)日：2003-07-01

申请号：US09274078

申请日：1999-03-22

Applicant: Paul M. Elliot ,  Ajaib S. Bhadare ,  Dyke T. Shaffer

Inventor： Paul M. Elliot ,  Ajaib S. Bhadare ,  Dyke T. Shaffer

IPC: H04L1228

CPC classification number: H04J3/1611 ,  H04J3/0685 ,  H04J2203/0025 ,  H04J2203/0026 ,  H04J2203/006 ,  H04L49/10 ,  H04L49/15 ,  H04L49/1523 ,  H04L49/254 ,  H04L49/40 ,  H04L49/552 ,  Y10S370/907

Abstract: A flexible cross-connect with a data plane is presented which allows the establishment of connections between network interfaces at any network interface card to another network interface on any other network interface card. The system can cross-connect connections at an STS-1 and VT 1.5 granularity, and allows the switching and routing of information in a data plane without the use of the cross connect fabric. This permits routing, bridging, and concentration of data services to be performed without burdening of the cross connect. For reliability, a range of protection configurations can be employed including 1:1, 1:5 and mixed 1:N protection. A backplane is used which provides point-to-point traces between each card and the cross connect unit, between each card and a timing, communications and control unit, and between the network interface cards themselves.

公开(公告)号：US20020097745A1

公开(公告)日：2002-07-25

申请号：US10100208

申请日：2002-03-18

Inventor： Stephen J. Brolin ,  Robert W. DeMarco

IPC: H04L012/26 ,  H04L012/28

CPC classification number: H04L49/557 ,  H04J3/0688 ,  H04J3/0691 ,  H04J2203/0012 ,  H04J2203/0017 ,  H04J2203/0021 ,  H04J2203/0025 ,  H04J2203/006 ,  H04L12/5601 ,  H04L49/1523 ,  H04L49/153 ,  H04L49/1553 ,  H04L49/25 ,  H04L49/30 ,  H04L49/3081 ,  H04L49/40 ,  H04L49/552 ,  H04L49/606 ,  H04L2012/5605 ,  H04L2012/5618 ,  H04L2012/5627 ,  H04L2012/5665 ,  H04Q11/0478

Abstract: An architecture for a SONET network element, such as a hybrid STM/ATM add-drop multiplexer. The disclosed system includes an interconnection system for a network element, including a line unit slot, a switch fabric slot, and two or more service unit slots. The line unit slot is connected as a hub to the switch fabric slot and the service unit slots in a first star interconnection configuration. The switch fabric slot is connected as a hub to the line unit slot and the service unit slots in a second star interconnection configuration. The star interconnection configurations provide fault isolation between different units, and allow for replacement of failed units without interfering with the links of other units to the hub. In a preferred embodiment, the switch fabric slot and one of the service unit slots comprise the same slot, thus permitting flexible configuration of the device within a minimal space. In a further illustrative embodiment, a control unit slot is provided in the interconnection system, and connected as a hub to the line unit slot, the switch fabric slot, and the service unit slots to form a third star interconnection configuration. A service unit is also disclosed, including a first backplane interface for connecting with an ATM star interconnect configuration within the network element, and a second backplane interface for connecting to an STM star interconnect configuration within said network element. The service unit further includes a third backplane interface to connect with a control star interconnect configuration within the network element.

Abstract translation: 用于SONET网元的架构，例如混合STM / ATM分插复用器。 所公开的系统包括用于网络元件的互连系统，包括线路单元时隙，交换矩阵时隙和两个或更多个服务单元时隙。 线路单元插槽作为集线器连接到交换矩阵槽，并且服务单元以第一星形互连配置插槽。 交换矩阵槽作为集线器连接到线路单元插槽，并且服务单元以第二星形互连配置插槽。 星形互连配置提供不同单元之间的故障隔离，并允许更换故障单元，而不会干扰其他单元到集线器的链路。 在优选实施例中，交换结构时隙和服务单元时隙中的一个包括相同的时隙，从而允许设备在最小空间内的灵活配置。 在另一说明性实施例中，控制单元插槽设置在互连系统中，并且作为集线器连接到线路单元插槽，交换矩阵插槽和服务单元插槽以形成第三星形互连配置。 还公开了一种服务单元，包括用于与网络元件内的ATM星形互连配置连接的第一背板接口和用于连接到所述网络元件内的STM星形互连配置的第二背板接口。 服务单元还包括第三背板接口，以与网络元件内的控制星形互连配置连接。