公开(公告)号：US07795925B2

公开(公告)日：2010-09-14

申请号：US12432426

申请日：2009-04-29

Applicant: Masazumi Marutani

Inventor： Masazumi Marutani

IPC: G01R25/00 ,  H03D13/00

CPC classification number: G01R25/08 ,  H03D13/001 ,  H03K5/26

Abstract: A phase difference detector for detecting a phase difference between input clocks which both have a same first frequency, including: a pulse width conversion unit for converting the input clocks into a phase difference signal indicating by a pulse width a phase difference between the input clocks; and a counter unit which samples a level of the phase difference signal using a reference clock having a second frequency which is slower than the first frequency, and counts the number of levels of the phase difference signal using a first weighting according to the sampled level of the phase difference signal. When the count value of the counter unit transits in a predetermined range, the phase difference between the input clocks is detected according to the first weighting.

Abstract translation: 一种相位差检测器，用于检测具有相同第一频率的输入时钟之间的相位差，包括：脉冲宽度转换单元，用于将输入时钟转换为指示脉冲宽度的输入时钟之间的相位差的相位差信号; 以及计数器单元，其使用具有比第一频率慢的第二频率的参考时钟对相位差信号的电平进行采样，并且使用根据采样电平的采样电平的第一加权来对相位差信号的电平数进行计数 相位差信号。 当计数器单元的计数值在预定范围内转变时，根据第一加权来检测输入时钟之间的相位差。

公开(公告)号：US07532040B1

公开(公告)日：2009-05-12

申请号：US11928080

申请日：2007-10-30

Applicant: Ram Kelkar ,  Grant P. Kesselring

Inventor： Ram Kelkar ,  Grant P. Kesselring

IPC: G01R23/02

CPC classification number: G01R23/005 ,  H03D13/001

Abstract: A frequency coincidence detection circuit for detecting frequency edges for each of a plurality of periodic digital signals. The circuit generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The circuit determines a signal coincidence of the coincidence windows. In another embodiment, a frequency coincidence detection method is provided. The method detects frequency edges for each of a plurality of periodic digital signals, generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The method determines a signal coincidence of the coincidence windows.

Abstract translation: 一种用于检测多个周期数字信号中的每一个的频率边缘的频率一致检测电路。 电路产生每个周期性数字信号的计数指示器，并将每个计数指示器与可编程灵敏度输入进行比较，以确定每个周期性数字信号中的相应一个的一致窗口。 电路确定符合窗口的信号重合。 在另一个实施例中，提供了一种频率一致检测方法。 该方法检测多个周期性数字信号中的每一个的频率边缘，为每个周期性数字信号产生计数指示符，并将每个计数指示符与可编程灵敏度输入进行比较，以确定每个周期数字信号中的每一个的相应窗口 周期性数字信号。 该方法确定符合窗口的信号重合。

公开(公告)号：US06661862B1

公开(公告)日：2003-12-09

申请号：US09579884

申请日：2000-05-26

Applicant: James S. Butcher

Inventor： James S. Butcher

IPC: H04D324

CPC classification number: H03D13/001 ,  H04L7/0012

Abstract: A digital delay line-based, timing relationship detector is operative to generate a K+L bit digital output code representative of a timing/phase offset between first and second low frequency clock signals. A first digital code generator generates a K-bit most significant phase word based upon the number of high frequency clock signals counted between transitions in the two low frequency clock signals. A second digital code generator generates an L-bit least significant phase word based upon the effective length of a delay line/shift register, through which a digital value associated with a transition in one of the two clock signals propagates, until a transition of the next occurring high frequency clock signal. The contents of a counter are incrementally changed in accordance with the number of stages of the multistage digital delay line/shift register through which the digital value has propagated. The L-bit least significant phase word is defined in accordance with the contents of the counter.

Abstract translation: 基于数字延迟线的定时关系检测器可操作以产生表示第一和第二低频时钟信号之间的定时/相位偏移的K + L位数字输出代码。 第一数字码发生器基于在两个低频时钟信号中的转换之间计数的高频时钟信号的数量来生成K位最高有效相位字。 第二数字码发生器基于延迟线/移位寄存器的有效长度生成L位最低有效相位字，通过该延迟线/移位寄存器与两个时钟信号中的一个信号中的转换相关联的数字值传播到 下一个出现的高频时钟信号。 计数器的内容根据数字值传播的多级数字延迟线/移位寄存器的级数逐步变化。 根据计数器的内容定义L位最低有效相位字。

公开(公告)号：US20030067354A1

公开(公告)日：2003-04-10

申请号：US09973979

申请日：2001-10-09

Inventor： Anatoliy V. Tsyrganovich

IPC: H03L007/00

CPC classification number: H03L7/085 ,  H03D13/001 ,  H03L7/091

Abstract: A filter using analog to digital conversion, digital filtering and oversampling noise reshaping is disclosed. Application of such a filter to a frequency locked oscillator is disclosed. Application of such a filter to an oscillator having a capability to synchronize with an external stimulus is disclosed.

公开(公告)号：US06392494B2

公开(公告)日：2002-05-21

申请号：US09115952

申请日：1998-07-15

Applicant: Masato Takeyabu ,  Akira Kikuchi ,  Toshiyuki Sakai

Inventor： Masato Takeyabu ,  Akira Kikuchi ,  Toshiyuki Sakai

IPC: H03L7087

CPC classification number: H03L7/0805 ,  G01R25/00 ,  H03D13/001 ,  H03L7/07 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089 ,  H03L7/0893 ,  H03L7/14 ,  H04L7/033

Abstract: A frequency comparator includes a circuit comparing, independently of a phase relationship between first and second clocks, frequencies of the first and second clocks and outputting first and second detection signals when the first clock has frequencies higher and lower than those of the second clock, respectively. The first and second detection signals are output for respective times based on a difference between the frequencies of the first and second clocks.

Abstract translation: 频率比较器包括电路，与第一和第二时钟之间的相位关系独立地比较第一和第二时钟的频率，并且当第一时钟分别具有高于和低于第二时钟的频率时，输出第一和第二检测信号 。 基于第一和第二时钟的频率之间的差，输出第一和第二检测信号各自的时间。

公开(公告)号：US5757868A

公开(公告)日：1998-05-26

申请号：US726727

申请日：1996-10-07

Applicant: James Robert Kelton ,  David Paul Gurney ,  Kevin Lynn Baum

Inventor： James Robert Kelton ,  David Paul Gurney ,  Kevin Lynn Baum

IPC: H03D13/00 ,  H03D3/18

CPC classification number: H03D13/001

Abstract: A digital phase detector 100 receives a limited input signal 108 and inputs it and a reference oscillation 112 into an EXCLUSIVE NOR gate 102. The output 110 of the EXCLUSIVE NOR gate 102 is input to a gated N-bit counter 104, which produces an N-bit representation of the magnitude of the phase 115 of the signal 108. A sign detector 105 determines the sign of the phase of the signal by sampling the resultant 110 and combines the magnitude of the phase 115 with the sign of the phase to produce a digital numeric representation of the phase of the signal 116.

Abstract translation: 数字相位检测器100接收受限输入信号108并将其输入和参考振荡112输入到异或非门102中。独占或非门102的输出110被输入到选通的N位计数器104，其产生N 表示信号10​​8的相位115的幅度。符号检测器105通过对结果110进行采样来确定信号的相位的符号，并且将相位115的幅度与相位的符号组合以产生相位 信号116的相位的数字数字表示。

公开(公告)号：US5539776A

公开(公告)日：1996-07-23

申请号：US158118

申请日：1993-11-24

Applicant: Ravi Subramanian

Inventor： Ravi Subramanian

IPC: H03D7/00 ,  H03D7/16 ,  H03D13/00 ,  H04L27/156 ,  H04L27/233 ,  H03D3/22

CPC classification number: H03D7/161 ,  H03D7/00 ,  H03D13/001 ,  H03D2200/005 ,  H03D2200/006 ,  H03D2200/007

Abstract: An intermediate frequency (IF) to baseband frequency signal converter for decoding an analog IF signal using phase information contained in the IF signal includes a first signal generator for generating an analog square wave signal from the IF signal. The signal converter also includes a second signal generator for generating a local phase reference signal, and a phase difference determinator for determining at a particular sampling interval a phase difference between a phase of the analog square wave signal and a phase of the local phase reference signal, wherein the phase difference represents a symbol which the signal converter has decoded from the IF signal.

Abstract translation: 使用包含在IF信号中的相位信息来解码模拟IF信号的基带频率信号转换器的中频（IF）包括用于从IF信号产生模拟方波信号的第一信号发生器。 信号转换器还包括用于产生局部相位参考信号的第二信号发生器和用于在特定取样间隔确定模拟方波信号的相位与局部相位参考信号的相位之间的相位差的相位差确定器 ，其中所述相位差表示所述信号转换器从所述IF信号解码的符号。

公开(公告)号：US5369374A

公开(公告)日：1994-11-29

申请号：US219020

申请日：1994-03-28

Applicant: Toshiharu Kojima

Inventor： Toshiharu Kojima

IPC: H03D7/00 ,  H03D7/16 ,  H03D13/00 ,  H04L27/233 ,  H04L27/22

CPC classification number: H04L27/2332 ,  H03D13/001 ,  H03D13/003 ,  H03D7/00 ,  H04L27/2337 ,  H03D2200/007 ,  H03D7/161 ,  H03D7/165

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to a phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement circuit 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision circuit. Alternatively, the phase detection circuit 400 for generating the relative phase signal may include: a half-period detection circuit 901 consisting of a delay element 401 and an exclusive OR element 402; a phase reference signal generation circuit 902 consisting of a modulo 2N counter 403; and a phase shift measurement circuit 903 consisting of a phase inversion corrector 500 and a D flip-flop array 404. The delay element 40 delays the relative phase signal by one symbol period and the subtractor 41 outputs the phase difference signal representing the phase transition over each symbol period of the received signal. The decision circuit 42 obtains The demodulated data from the phase difference signal.

Abstract translation: 在差分检测解调器中，接收信号首先由限幅放大器10量化，然后由包括：异或元件51的变频器50进行频率转换; 由移位寄存器53和加法器54组成的运行平均发生器52; 和比较器55.响应于频率转换器50的输出，相位比较器60相对于相位参考信号输出表示频率转换之后的接收信号的相移的相对相位信号。 相位比较器60包括：异或元件61; 由加法器63和D触发器阵列64和65组成的绝对相移测量电路62; 以及用作相移极性判定电路的D触发器66。 或者，用于产生相对相位信号的相位检测电路400可以包括：由延迟元件401和异或元件402组成的半周期检测电路901; 由2N模计数器403组成的相位参考信号发生电路902; 以及由相位反相校正器500和D触发器阵列404组成的相移测量电路903.延迟元件40将相对相位信号延迟一个符号周期，并且减法器41输出表示相位转变的相位差信号 接收信号的每个符号周期。 判定电路42从相位差信号中获得解调数据。

公开(公告)号：US5248969A

公开(公告)日：1993-09-28

申请号：US915115

申请日：1992-07-17

Applicant: Bhum C. Lee ,  Jung S. Kim ,  Kwon C. Park

Inventor： Bhum C. Lee ,  Jung S. Kim ,  Kwon C. Park

IPC: H03M5/12 ,  H03D13/00 ,  H03M5/06 ,  H03M5/14 ,  H04L7/033 ,  H04L25/49

CPC classification number: H03M5/145 ,  H04L25/4912 ,  H04L7/033 ,  H03D13/001

Abstract: A phase comparing and CMI/NRZ decoding apparatus for accomplishing bit synchronization of CMI data by producing rising transition or falling transition of the clock pulse at the center of unit bit interval of incoming CMI data, by use of the clock pulse having a period equivalent to 2 unit bit intervals of CMI data, and for realizing stable decoding of CMI data to NRZ data. This apparatus is implemented by means of a data output means 2, a clock pulse generating means 1 for generating in-phase and inverse-phase pulses, a inter-transitions time interval information output means 3 for outputting information about line interval between the data transition and the clock pulse transition, a reference pulse generating means 4, a falling transition detecting and 3-step half-period shifting means 6, a rising transition detecting and 2-step half-period shifting means 5, a CMI/NRZ decoding circuit 7 and a code violation detecting means 8.

Abstract translation: 一种相位比较和CMI / NRZ解码装置，用于通过使用具有相当于时钟脉冲周期的时钟脉冲的时钟脉冲来产生CMI数据的位同步，通过产生时钟脉冲在进入CMI数据的单位比特间隔的中心处的上升转换或下降转换 CMI数据的2个单位位间隔，用于实现CMI数据到NRZ数据的稳定解码。 该装置通过数据输出装置2，用于产生同相和反相脉冲的时钟脉冲发生装置1来实现;转换间间隔信息输出装置3，用于输出关于数据转换之间的行间隔的信息 时钟脉冲转移，参考脉冲发生装置4，下降转变检测和三步半周期移位装置6，上升转变检测和两步半周期移位装置5，CMI / NRZ解码电路7 以及代码违规检测单元8。

公开(公告)号：US20240195424A1

公开(公告)日：2024-06-13

申请号：US18063809

申请日：2022-12-09

Applicant: Allegro MicroSystems, LLC

Inventor： Florencia Ferrer ,  Lucas Intile ,  Juan Manuel Cesaretti ,  Nicolás Rigoni

IPC: H03L7/099 ,  H03D13/00 ,  H03K3/12

CPC classification number: H03L7/0991 ,  H03D13/001 ,  H03K3/12

Abstract: Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.