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11.SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE AND ITS METHODS OF FABRICATION 审中-公开
Title translation: 具有嵌入式DIE的半导体封装及其制造方法公开(公告)号:US20150050781A1
公开(公告)日:2015-02-19
申请号:US14529881
申请日:2014-10-31
Applicant: John S. Guzek , Javier Soto Gonzalez , Nicholas R. Watts , Ravi K Nalla
Inventor: John S. Guzek , Javier Soto Gonzalez , Nicholas R. Watts , Ravi K Nalla
IPC: H01L23/00 , H01L21/56 , H01L21/768
CPC classification number: H01L24/11 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L21/768 , H01L23/315 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/26 , H01L24/27 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/03 , H01L25/074 , H01L25/105 , H01L25/117 , H01L2221/68345 , H01L2224/03462 , H01L2224/0401 , H01L2224/11831 , H01L2224/12105 , H01L2224/13025 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/24227 , H01L2224/26 , H01L2224/27312 , H01L2224/2732 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/821 , H01L2224/83192 , H01L2224/83874 , H01L2224/92132 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2924/40252 , H01L2924/40407 , H01L2924/40501 , H05K1/185 , H05K3/4682 , H05K2201/10477 , H05K2203/0152 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.
Abstract translation: 本发明的实施例描述了具有嵌入式管芯的半导体封装。 该半导体封装包括一个包含嵌入式裸片的无芯基板。 半导体封装提供管芯堆叠或封装堆叠功能。 此外,本发明的实施例描述了一种使组装成本最小化的半导体封装的制造方法。