公开(公告)号：US06693834B1

公开(公告)日：2004-02-17

申请号：US10448727

申请日：2003-05-29

Applicant: Tie Jiang Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo Ching Jiang

Inventor： Tie Jiang Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo Ching Jiang

IPC: G11C700

CPC classification number: H01L27/10829 ,  G03F7/70633 ,  G03F7/70658 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  H01L22/34 ,  H01L27/0207 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method and device for detecting alignment of bit lines and bit line contacts in DRAM devices. In the present invention, the test device is disposed in the scribe line region and is formed by the same masks and process as the bit lines and bit line contacts in the memory regions simultaneously. The memory deices and test may have the same alignment shift between bit line contacts and bit line due to use of the same masks and process. Thus, alignment of bit lines and bit line contacts in the memory region is determined according to two resistances (R1 and R2) detected by the test device. Further, the alignment shift can be obtained by Δ ⁢   ⁢ W = R MO × L × ( 1 R 1 - 1 R 2 ) , wherein RMO is the resistance per surface area of the bit lines, and L is the length of the bar-type bit line contacts in the test device.

Abstract translation: 一种用于检测DRAM器件中位线和位线触点的对准的方法和装置。 在本发明中，测试装置设置在划线区域中，并且与存储区域中的位线和位线接触同样的掩模和处理形成。 由于使用相同的掩模和过程，存储器和测试可能在位线触点和位线之间具有相同的对准位移。 因此，根据由测试装置检测到的两个电阻（R1和R2）来确定存储器区域中位线和位线触点的对准。 此外，通过其中RMO是位线的每个表面积的电阻，并且L是测试装置中条形位线触点的长度，可以获得对准偏移。

公开(公告)号：US20130001658A1

公开(公告)日：2013-01-03

申请号：US13174800

申请日：2011-07-01

Applicant: Tieh-Chiang Wu ,  Yu-Teh Chiang ,  Yu-Wei Ting

Inventor： Tieh-Chiang Wu ,  Yu-Teh Chiang ,  Yu-Wei Ting

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/7853

Abstract: A method of fabricating a corner transistor is described. An isolation structure is formed in a substrate to define an active region. A treating process is performed to make the substrate in the active region have sharp corners at top edges thereof. The substrate in the active region is covered by a gate dielectric layer. A gate conductor is formed over the gate dielectric layer. A source region and a drain region are formed in the substrate beside the gate conductor.

Abstract translation: 描述制造角晶体的方法。 在衬底中形成隔离结构以限定有源区。 执行处理工艺以使有源区域中的衬底在其顶部边缘处具有锐角。 有源区中的衬底被栅介电层覆盖。 栅极导体形成在栅极介电层上。 源极区域和漏极区域形成在栅极导体旁边的衬底中。

公开(公告)号：US20090189251A1

公开(公告)日：2009-07-30

申请号：US12101161

申请日：2008-04-11

Applicant: Yu-Wei Ting ,  Shing-Hwa Renn ,  Yu-Teh Chiang ,  Chung-Ren Li ,  Tieh-Chiang Wu

Inventor： Yu-Wei Ting ,  Shing-Hwa Renn ,  Yu-Teh Chiang ,  Chung-Ren Li ,  Tieh-Chiang Wu

IPC: H01L29/92

CPC classification number: H01L29/66181 ,  H01L28/87

Abstract: A capacitor structure for a pumping circuit includes a substrate, a U-shaped bottom electrode in the substrate, a T-shaped top electrode in the substrate and a dielectric layer disposed between the U-shaped bottom and T-shaped top electrode. The contact area of the capacitor structure between the U-shaped bottom and T-shaped top electrode is extended by means of the cubic engagement of the U-shaped bottom electrode and the T-shaped top electrode.

Abstract translation: 用于泵浦电路的电容器结构包括衬底，衬底中的U形底电极，衬底中的T形顶电极和设置在U形底部和T形顶电极之间的电介质层。 U形底部电极和T形顶部电极之间的电容器结构的接触面积通过U形底部电极和T形顶部电极的三次接合而延伸。

公开(公告)号：US20060128041A1

公开(公告)日：2006-06-15

申请号：US11339687

申请日：2006-01-26

Applicant: Chien-Chang Huang ,  Tie-Jiang Wu ,  Chin-Ling Huang ,  Yu-Wei Ting ,  Bo-Ching Jiang

Inventor： Chien-Chang Huang ,  Tie-Jiang Wu ,  Chin-Ling Huang ,  Yu-Wei Ting ,  Bo-Ching Jiang

IPC: H01L21/66

CPC classification number: G03F9/7088 ,  G03F7/70633 ,  G03F7/70658 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.

公开(公告)号：US07015050B2

公开(公告)日：2006-03-21

申请号：US10718612

申请日：2003-11-24

Applicant: Chien-Chang Huang ,  Tie-Jiang Wu ,  Chin-Ling Huang ,  Yu-Wei Ting ,  Bo-Ching Jiang

Inventor： Chien-Chang Huang ,  Tie-Jiang Wu ,  Chin-Ling Huang ,  Yu-Wei Ting ,  Bo-Ching Jiang

IPC: H01L21/00

CPC classification number: G03F9/7088 ,  G03F7/70633 ,  G03F7/70658 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.

Abstract translation: 提供了用于确定在集成电路制造工艺中发生的不对准的测试结构和测试方法。 测试结构包括具有第一测试结构和第二测试结构的第一导电层，其上的电介质层和介电层上的第二导电层。 第二导电层包括在第一方向和第二方向上分别与第一测试结构和第二测试结构的一部分重叠的第三测试结构和第四测试结构。 第一方向与第二方向相反。 该方法包括测量第一和第二导电层之间的电特性以计算由不对准引起的偏移量的步骤。

公开(公告)号：US06875654B2

公开(公告)日：2005-04-05

申请号：US10730674

申请日：2003-12-08

Applicant: Tieh Chiang Wu ,  Chien-Chang Huang ,  Chin-Ling Huang ,  Bo Ching Jiang ,  Yu-Wei Ting

Inventor： Tieh Chiang Wu ,  Chien-Chang Huang ,  Chin-Ling Huang ,  Bo Ching Jiang ,  Yu-Wei Ting

IPC: D02G3/00 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC classification number: H01L27/0207 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10876

Abstract: A memory device and fabricating method thereof. In the memory device of the present invention, a substrate has a plurality of deep trenches, wherein the deep trenches formed in the adjacent rows are staggered. A deep trench capacitor and a control gate are disposed in each deep trench successively. Word lines are disposed on the control gates respectively, and each word line is electrically coupled to the control gate thereunder. Diffusion regions are disposed in the substrate and surrounding the deep trenches respectively to serve as sources of vertical transistors. Each diffusion region is electrically connected to the surrounding deep trench capacitor. Active areas are disposed on the rows of the control gates respectively along a second direction. The regions where each active area overlaps the control gates have at least one indentation.

公开(公告)号：US08552478B2

公开(公告)日：2013-10-08

申请号：US13174800

申请日：2011-07-01

Applicant: Tieh-Chiang Wu ,  Yu-Teh Chiang ,  Yu-Wei Ting

Inventor： Tieh-Chiang Wu ,  Yu-Teh Chiang ,  Yu-Wei Ting

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/7853

Abstract: A method of fabricating a corner transistor is described. An isolation structure is formed in a substrate to define an active region. A treating process is performed to make the substrate in the active region have sharp corners at top edges thereof. The substrate in the active region is covered by a gate dielectric layer. A gate conductor is formed over the gate dielectric layer. A source region and a drain region are formed in the substrate beside the gate conductor.

Abstract translation: 描述制造角晶体的方法。 在衬底中形成隔离结构以限定有源区。 执行处理工艺以使有源区域中的衬底在其顶部边缘处具有锐角。 有源区中的衬底被栅介电层覆盖。 栅极导体形成在栅极介电层上。 源极区域和漏极区域形成在栅极导体旁边的衬底中。

公开(公告)号：US07381575B2

公开(公告)日：2008-06-03

申请号：US11096836

申请日：2005-03-30

Applicant: Tie Jiang Wu ,  Chien-Chang Huang ,  Bo Ching Jiang ,  Yu-Wei Ting ,  Chin-Ling Huang

Inventor： Tie Jiang Wu ,  Chien-Chang Huang ,  Bo Ching Jiang ,  Yu-Wei Ting ,  Chin-Ling Huang

IPC: H01L21/66

CPC classification number: H01L27/10876 ,  G11C11/401 ,  G11C29/36 ,  G11C2029/5002 ,  H01L22/34 ,  H01L27/10841

Abstract: A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.

Abstract translation: 一种用于检测具有垂直晶体管的DRAM器件中的有源区和存储单元结构的对准的测试装置和方法。 在测试装置中，设置在划线区域中的并行第一和第二存储单元结构各自具有深沟槽电容器和晶体管结构。 有源区域设置在第一和第二存储单元结构之间。 活动区域与第一和第二存储单元结构重叠预定宽度。 第一和第二导电焊盘分别设置在第一存储单元结构的两端，第三和第四导电焊盘分别设置在第一存储单元结构的两端。

公开(公告)号：US06984534B2

公开(公告)日：2006-01-10

申请号：US10809999

申请日：2004-03-26

Applicant: Tie Jiang Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo Ching Jiang ,  Chin-Ling Huang

Inventor： Tie Jiang Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo Ching Jiang ,  Chin-Ling Huang

IPC: G01R31/26

CPC classification number: G11C29/50008 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025

Abstract: Method for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal, and a test device thereof. In the present invention a plurality of memory cells are formed in the memory area and at least one test device is formed in the scribe line region simultaneously. A first resistance and a second resistance are detected by the test device. Normal alignment of the bit line and the bar-type active area of the test device is determined according to the first resistance and the second resistance. Finally, whether the alignment of the bit line contacts and the active areas in memory areas is normal is determined according to whether the alignment of the bit line contact and bar-type active area of the test device is normal.

Abstract translation: 用于检测DRAM装置中位线接触和有源区的对准是否正常的方法及其测试装置。 在本发明中，在存储区域中形成多个存储单元，同时在划线区域中形成至少一个测试装置。 第一电阻和第二电阻由测试装置检测。 根据第一电阻和第二电阻确定测试装置的位线和条形有源区域的正常对准。 最后，根据测试装置的位线接触和条形有源区域的对准是否正常来确定位线触点的对齐和存储区域中的有效区域是否正常。

公开(公告)号：US06902942B2

公开(公告)日：2005-06-07

申请号：US10613175

申请日：2003-07-03

Applicant: Tie Jiang Wu ,  Chien-Chang Huang ,  Bo Ching Jiang ,  Yu-Wei Ting ,  Chin-Ling Huang

Inventor： Tie Jiang Wu ,  Chien-Chang Huang ,  Bo Ching Jiang ,  Yu-Wei Ting ,  Chin-Ling Huang

IPC: H01L21/8242 ,  H01L23/544 ,  H01L27/108 ,  H01L21/66

CPC classification number: H01L27/10864 ,  H01L22/34 ,  H01L27/10841 ,  H01L27/10891

Abstract: A test device and method for detecting alignment of word lines and deep trench capacitors in DRAM devices with vertical transistors. In the test device, an active area is disposed in the scribe line region. An H-type deep trench capacitor is disposed in the active area, and has parallel first and second portions and a third portion. Each of the first and second portions has a center and two ends. The third portion is disposed between the centers of the first and second portions. First to fourth conductive pads are disposed on the two ends of the first and second portions respectively. A bar-type conductive pad is disposed between the first and second portions, having a center aligned with a center of the third portion.

Abstract translation: 一种用于检测具有垂直晶体管的DRAM器件中的字线和深沟槽电容器的对准的测试装置和方法。 在测试装置中，有效区域设置在划线区域中。 H型深沟槽电容器设置在有源区域中，并且具有平行的第一和第二部分以及第三部分。 第一和第二部分中的每一个具有中心和两端。 第三部分设置在第一和第二部分的中心之间。 第一至第四导电焊盘分别设置在第一和第二部分的两端。 棒状导电垫设置在第一和第二部分之间，具有与第三部分的中心对准的中心。