公开(公告)号：US10825541B1

公开(公告)日：2020-11-03

申请号：US16150064

申请日：2018-10-02

Applicant: Xilinx, Inc.

Inventor： Henry Fu ,  Weiguang Lu ,  Karthy Rajasekharan

IPC: G11C29/10 ,  G11C29/36 ,  G11C29/38

Abstract: Examples herein describe a self-test process where an integrated circuit includes a test controller responsible for testing a plurality of frames in the memory of an integrated circuit. The test controller can receive a test pattern which the controller duplicates and stores in each of the plurality of frames. However, frames may be non-uniform meaning the frames have varying sizes. As such, some of the frames may only store parts of the test pattern rather than all of it. In any case, the test controller reads out the stored data and generates a checksum which can then be compared to a baseline checksum generated from simulating the integrated circuit using design code to determine whether there is a manufacturing defect in the frames.

公开(公告)号：US20200274536A1

公开(公告)日：2020-08-27

申请号：US16285588

申请日：2019-02-26

Applicant: Xilinx, Inc.

Inventor： Rafael C. Camarota ,  Ui S. Han ,  Weiguang Lu

IPC: H03K19/177 ,  G06F17/50

Abstract: Examples described herein provide for a boundary logic interface (BLI) to a programmable logic region in an integrated circuit (IC), and methods for operating such IC. An example IC includes a programmable logic region and boundary logic interfaces. The programmable logic region includes columns of interconnect elements disposed between columns of logic elements. The boundary logic interfaces are at respective ends of and communicatively connected to the columns of interconnect elements. The boundary logic interfaces are outside of a boundary of the programmable logic region. A first boundary logic interface (BLI) of the boundary logic interfaces is configured to be communicatively connected to an exterior circuit. The first BLI includes an interface configured to communicate a signal between the exterior circuit and the programmable logic region.

公开(公告)号：US20200241770A1

公开(公告)日：2020-07-30

申请号：US16262420

申请日：2019-01-30

Applicant: Xilinx, Inc.

Inventor： Subodh Kumar ,  David P. Schultz ,  Weiguang Lu ,  Michelle Zeng

IPC: G06F3/06

Abstract: Embodiments herein describe a reconfigurable integrated circuit (IC) where data can be retained in memory when performing a partial reconfiguration. Partial reconfiguration includes reconfiguring programmable logic in the IC while certain functions of the IC remain operational or active. In one embodiment, the reconfigurable IC includes control logic for saving or retaining data in the IC during a partial reconfiguration. That is, rather than clearing the memory elements, the user can specify that the memory blocks containing certain data should be retained while the other memory blocks can be cleared. In this manner, the data can be retained in the IC during a partial reconfiguration which saves time, power, and cost. Once partial reconfiguration is complete, the newly configured programmable logic can retrieve and process the saved data from the on-chip memory.

公开(公告)号：US10666266B1

公开(公告)日：2020-05-26

申请号：US16212566

申请日：2018-12-06

Applicant: Xilinx, Inc.

Inventor： Karthy Rajasekharan ,  Weiguang Lu

IPC: H03K19/1776 ,  H03K19/17724 ,  H03K19/17704

Abstract: Apparatus and method relate generally to a configuration engine. In one such configuration engine for a programmable circuit, a frame counter includes a cascade of frame incrementer circuits associated with columns for a row of circuit blocks. Each frame incrementer circuit is configured to provide frame sums for frames associated with the circuit blocks. The frame counter is configured to sequentially add the frame sums for the columns to provide corresponding frame totals respectively for circuit types of the circuit blocks. A termination circuit is configured to multiplex the frame totals onto a data bus. A row controller is configured to initiate the frame counter and to selectively access the frame totals provided to the data bus.

公开(公告)号：US10305511B1

公开(公告)日：2019-05-28

申请号：US15990151

申请日：2018-05-25

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Weiguang Lu ,  Priyanka Agrawal ,  Jun Liu ,  Sourabh Goyal ,  David Robinson

IPC: H03M7/46 ,  G06F17/50

Abstract: Decompressing a data set includes inputting data units to a decompression circuit and comparing each input data unit to a run value and to a substitute value. In response to the data unit being not equal to the run value or the substitute value, the decompression circuit outputs the value of the input data unit; in response to the input data unit having the run value and a succeeding data unit having a value N not equal to zero or one, the decompression circuit outputs multiple data units having the run value based on the value N; in response to input data unit having the substitute value, the decompression circuit outputs one data unit having the run value; and in response to one input data unit having the run value and a succeeding data unit equal to zero or one, the decompression circuit outputs one data unit of the substitute value.