公开(公告)号：US20230055704A1

公开(公告)日：2023-02-23

申请号：US17408218

申请日：2021-08-20

Applicant: Xilinx, Inc.

Inventor： Sebastian Turullols ,  Kyle Corbett ,  Sudipto Chakraborty ,  Siva Santosh Kumar Pyla ,  Ravinder Sharma ,  Kaustuv Manji ,  Jayaram PVSS ,  Stephen P. Rozum ,  Ch Vamshi Krishna ,  Susheel Puthana

IPC: G06F30/392 ,  G06F30/3953 ,  G06F30/398

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

公开(公告)号：US10713404B1

公开(公告)日：2020-07-14

申请号：US16218133

申请日：2018-12-12

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Anurag Dubey ,  Pramod Chandraiah ,  Stephen P. Rozum ,  Hem C. Neema

IPC: G06F30/00 ,  G06F30/34 ,  G06F11/36 ,  G06F9/445

Abstract: Embodiments herein describe reconfigurable integrated circuits (ICs) which include programmable logic that can be configured to perform a user task. In one embodiment, the programmable logic is configured as an accelerator. The user may want to gather debug data or profiling data when executing the accelerator. Rather than using debug/profile circuitry disposed in a static region of the IC, the user can provide preferences to a linker which then dynamically configures debug/profile circuitry in a dynamic region of the IC. That is, based on user preferences, the linker can generate customized debug/profile circuitry for monitoring the performance of the accelerator. In one embodiment, the debug/profile circuitry is implemented in the dynamic region of the IC and is tailored to user preferences rather than relying on static, or fixed, debug/profile circuitry. Moreover, the user can retrieve the debug/profiling data on demand using a call back and a device driver.

公开(公告)号：US10216217B1

公开(公告)日：2019-02-26

申请号：US15382390

申请日：2016-12-16

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Sudipto Chakraborty ,  Fei Rui ,  Stephen P. Rozum ,  Yenpang Lin ,  Yau-Tsun S. Li ,  Sumit Roy

IPC: G06F1/00 ,  G06F1/08

Abstract: Hardware acceleration for a kernel can include selecting, using a processor, a kernel, determining, using the processor, a clock frequency for the selected kernel, and programming, using the processor, a clock circuit to generate a clock signal having a clock frequency compatible with the clock frequency of the selected kernel. Using the processor, the selected kernel can be implemented as a kernel circuit within a region of programmable circuitry. The kernel circuit can be clocked using the clock signal from the clock circuit having the compatible clock frequency.

公开(公告)号：US09864828B1

公开(公告)日：2018-01-09

申请号：US14857634

申请日：2015-09-17

Applicant: Xilinx, Inc.

Inventor： Susheel Kumar Puthana ,  Stephen P. Rozum ,  Sudipto Chakraborty ,  David A. Knol ,  Yong Li ,  Fernando J. Martinez Vallina ,  Sonal Santan ,  Nabeel Shirazi ,  Salil R. Raje ,  Ethan T. Parker ,  Suman Kumar Timmireddy ,  Heera Nand

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5072

Abstract: Implementing hardware accelerators using programmable integrated circuits may include performing, using a processor, a design flow on a static circuit design. The static circuit design may specify a region reserved for a hardware accelerator and a static region comprising interface circuitry configured to couple the hardware accelerator with an external node. The design flow may generate an implemented static circuit design. Metadata describing the interface circuitry may be generated using a processor. A device support archive including the implemented static circuit design and the metadata may be written, using the processor, to a computer readable storage medium.