公开(公告)号：US10216217B1

公开(公告)日：2019-02-26

申请号：US15382390

申请日：2016-12-16

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Sudipto Chakraborty ,  Fei Rui ,  Stephen P. Rozum ,  Yenpang Lin ,  Yau-Tsun S. Li ,  Sumit Roy

IPC: G06F1/00 ,  G06F1/08

Abstract: Hardware acceleration for a kernel can include selecting, using a processor, a kernel, determining, using the processor, a clock frequency for the selected kernel, and programming, using the processor, a clock circuit to generate a clock signal having a clock frequency compatible with the clock frequency of the selected kernel. Using the processor, the selected kernel can be implemented as a kernel circuit within a region of programmable circuitry. The kernel circuit can be clocked using the clock signal from the clock circuit having the compatible clock frequency.

公开(公告)号：US10108769B1

公开(公告)日：2018-10-23

申请号：US15295911

申请日：2016-10-17

Applicant: Xilinx, Inc.

Inventor： Yau-Tsun S. Li ,  Grigor S. Gasparyan

IPC: G06F17/50

Abstract: Designing circuits can include, within a circuit design, detecting, using a processor, a high fan-out net having loads with a same timing requirement, wherein the circuit design is technology specific for a target integrated circuit (IC), determining, using the processor, a region having a predetermined shape and an area sized to fit loads of the high fan-out net within the region on the target IC, and determining, using the processor, a delay of the high fan-out net based upon a distance from a center of the region to an edge of the region. Designing circuits can also include assigning, using the processor, the delay to the high fan-out net.

公开(公告)号：US08972920B1

公开(公告)日：2015-03-03

申请号：US14178035

申请日：2014-02-11

Applicant: Xilinx, Inc.

Inventor： Grigor S. Gasparyan ,  Dinesh D. Gaitonde ,  Yau-Tsun S. Li

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/50 ,  G06F17/5031 ,  G06F17/5054 ,  G06F2217/84

Abstract: Re-budgeting connections includes detecting a budget event for a circuit design and, responsive to detecting the budget event, calculating, using a processor, a delta for a selected combinatorial circuit element of the circuit design using an incoming slack and an outgoing slack of the selected combinatorial circuit element. Using the processor, a delay budget for a connection of the selected combinatorial circuit element is adjusted using the delta responsive to detecting the budget event.

Abstract translation: 重新预算连接包括检测用于电路设计的预算事件，并且响应于检测到预算事件，使用处理器计算电路设计的所选择的组合电路元件的增量，使用输入的松弛和输出的松弛 选择的组合电路元件。 使用处理器，使用响应于检测预算事件的增量来调整所选择的组合电路元件的连接的延迟预算。

公开(公告)号：US08769461B1

公开(公告)日：2014-07-01

申请号：US13742179

申请日：2013-01-15

Applicant: Xilinx, Inc.

Inventor： Yau-Tsun S. Li ,  Anup K. Sultania ,  E. Syama Sundara Reddy

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: Processing a circuit design for implementation on a target device includes, for a first driver that is a driver of a net having a plurality of loads, selecting a second driver that is a driver of the first driver. A representation of a rectilinear Steiner arborescence (RSA) tree is generated from the second driver and the plurality of loads. The RSA tree includes nodes representative of the plurality of loads and a plurality of Steiner points. A subset of the plurality of Steiner points in the RSA tree is selected for disposing respective replicated instances of the first driver. The respective replicated instances of the first driver are assigned to locations on the target device associated with the subset of Steiner points. The connections from each of the respective replicated instances of the first driver are assigned to a respective subset of the plurality of loads.

Abstract translation: 处理用于在目标设备上实现的电路设计包括对于作为具有多个负载的网络的驱动器的第一驱动器，选择作为第一驱动器的驱动器的第二驱动器。 从第二个驱动器和多个负载产生一个直线Steiner子波（RSA）树的表示。 RSA树包括表示多个负载的节点和多个Steiner点。 选择RSA树中的多个Steiner点的子集用于布置第一驱动器的各个复制实例。 将第一驱动程序的各个复制实例分配给与Steiner子集的子集相关联的目标设备上的位置。 来自第一驱动器的相应复制实例中的每一个的连接被分配给多个负载的相应子集。