公开(公告)号：US09455760B1

公开(公告)日：2016-09-27

申请号：US14791096

申请日：2015-07-02

Applicant: Xilinx, Inc.

Inventor： Christopher H. Dick ,  Hemang M. Parekh ,  Hongzhi Zhao ,  Vincent C. Barnes

IPC: H04B1/04 ,  H04B1/62

CPC classification number: H04B1/62 ,  H03F1/3247 ,  H03F3/245 ,  H03F2201/3233 ,  H04B1/0475 ,  H04B2001/0425 ,  H04L25/03343 ,  H04L27/368

Abstract: Apparatus, method therefor, generally related to signal preconditioning. In such an apparatus, a signal classifier block and a delay block are commonly coupled for receiving an input signal. The delay block is for providing a delayed version of the input signal. The signal classifier block is for classifying the input signal and generating a configuration signal having configuration information for digital predistortion (“DPD”) engine parameterization in response to the input signal classification. A DPD engine is for receiving the delayed version of the input signal and the configuration signal and for providing a predistorted output signal.

Abstract translation: 装置及其方法一般与信号预处理有关。 在这种装置中，信号分类器块和延迟块通常被耦合用于接收输入信号。 延迟块用于提供输入信号的延迟版本。 信号分类器块用于对输入信号进行分类，并产生具有响应于输入信号分类的用于数字预失真（“DPD”）引擎参数化的配置信息的配置信号。 DPD引擎用于接收输入信号和配置信号的延迟版本并提供预失真的输出信号。