公开(公告)号：US10049177B1

公开(公告)日：2018-08-14

申请号：US14792953

申请日：2015-07-07

Applicant: Xilinx, Inc.

Inventor： Benjamin S. Devlin ,  Ilya K. Ganusov

IPC: G06F17/50

Abstract: A circuit for reducing power consumed by routing clock signals in an integrated circuit is described. The circuit comprises a clock routing network comprising a clock row coupled to receive an input clock signal having a first clock frequency and a plurality of clock branches coupled to the clock row; and a plurality of circuit blocks coupled to the plurality of clock branches, each circuit block having a clock conversion circuit and a register; wherein the clock conversion circuit is programmable to generate clock pulses of an internal clock signal, coupled to the register, having a second frequency that is greater than the first frequency. A method of reducing power consumed by routing clock signals in an integrated circuit is also disclosed.

公开(公告)号：US09900027B1

公开(公告)日：2018-02-20

申请号：US14693415

申请日：2015-04-22

Applicant: Xilinx, Inc.

Inventor： Benjamin S. Devlin

IPC: H03M13/35 ,  H04L1/00 ,  H04L12/26

CPC classification number: H03M13/353 ,  H04L1/004 ,  H04L41/0813 ,  H04L43/0823 ,  H04L43/0847

Abstract: A method, non-transitory computer readable medium and circuit for detecting and correcting errors in a communication channel are disclosed. The circuit includes error monitoring logic for monitoring the communication channel in real time for a performance metric, a fixed-operating point encoder/decoder coupled to the error monitoring logic for generating a bit stream containing redundant data used for the detecting and correcting, a reconfigurable controller coupled to the fixed-operating point encoder/decoder, wherein a configuration of the reconfigurable controller determines an amount of the redundant data contained in the bit stream, and a data structure implemented in a logic fabric of the circuit and coupled to the error monitoring logic, for generating the configuration of the reconfigurable controller responsive to a value of the performance metric controller.

公开(公告)号：US09842187B1

公开(公告)日：2017-12-12

申请号：US15082993

申请日：2016-03-28

Applicant: Xilinx, Inc.

Inventor： Jindrich Zejda ,  Atul Srinivasan ,  Ilya K. Ganusov ,  Walter A. Manaker, Jr. ,  Benjamin S. Devlin ,  Satish B. Sivaswamy

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5054 ,  G06F2217/84

Abstract: Approaches for processing a circuit design include determining pin slack values for pins of the circuit elements in the circuit design. A processor selects a subset of endpoints based on pin slack values of the endpoints being in a critical slack range and determines startpoints of the circuit design that are in respective critical fanin cones. For each endpoint of the subset, the processor determines an arrival time from each startpoint in the respective critical fanin cone and determines for each startpoint-endpoint pair, a respective set of constraint values as a function of the respective arrival time from the startpoint. The processor generates a graph in the memory circuit from the startpoint-endpoint pairs. First nodes in the graph represent the startpoints and second nodes in the graph represent the endpoints, and values in the respective set of constraint values are associated with edges that connect the nodes.

公开(公告)号：US09531351B1

公开(公告)日：2016-12-27

申请号：US14835571

申请日：2015-08-25

Applicant: Xilinx, Inc.

Inventor： Benjamin S. Devlin ,  Ilya K. Ganusov

IPC: H03K3/289 ,  H03K3/037

CPC classification number: H03K3/0372

Abstract: In an example implementation, a circuit includes first and second latch circuits. A circuit coupled to the first and second latch circuits is configured to provide a first clock signal to the clock input node of the second latch circuit and provide a second clock signal that is an inversion of the first clock signal to the clock input node of the first latch circuit. The circuit includes a first multiplexer having a first input node coupled to a data output node of the first latch circuit, a second input node coupled to a data input node of the first latch circuit, and an output node coupled to a data input node of the second latch circuit. The circuit also includes a second multiplexer having a first input node coupled to the data output node of the first latch circuit and a second input node coupled to a data output node of the second latch circuit.

Abstract translation: 在示例实现中，电路包括第一和第二锁存电路。 耦合到第一和第二锁存电路的电路被配置为向第二锁存电路的时钟输入节点提供第一时钟信号，并提供第二时钟信号，该第二时钟信号是将第一时钟信号反转到时钟输入节点 第一锁存电路。 电路包括第一多路复用器，其具有耦合到第一锁存电路的数据输出节点的第一输入节点，耦合到第一锁存电路的数据输入节点的第二输入节点，以及耦合到第一锁存电路的数据输入节点的输出节点 第二锁存电路。 电路还包括第二多路复用器，其具有耦合到第一锁存电路的数据输出节点的第一输入节点和耦合到第二锁存电路的数据输出节点的第二输入节点。

公开(公告)号：US09496871B1

公开(公告)日：2016-11-15

申请号：US14462370

申请日：2014-08-18

Applicant: Xilinx, Inc.

Inventor： Benjamin S. Devlin ,  Brian C. Gaide ,  Santosh Kumar Sood

IPC: G11C5/14 ,  H03K19/00 ,  H03K19/177

CPC classification number: H03K19/0016 ,  G11C5/063 ,  G11C5/147 ,  H03K19/17748

Abstract: An integrated circuit includes: a voltage rail; voltage control circuitry coupled to the voltage rail; and a circuit block coupled to the voltage control circuitry; wherein the voltage control circuitry is selectively configurable to operate the circuit block in at least a first mode of operation and a second mode of operation; wherein in the first mode of operation, the circuit block receives a voltage that is substantially the same as a voltage of the voltage rail; and wherein in the second mode of operation, the circuit block receives a voltage that is less than the voltage of the voltage rail by a threshold voltage.

Abstract translation: 集成电路包括：电压轨; 耦合到电压轨的电压控制电路; 以及耦合到所述电压控制电路的电路块; 其中所述电压控制电路被选择性地配置为在至少第一操作模式和第二操作模式中操作所述电路块; 其中在所述第一操作模式中，所述电路块接收与所述电压轨的电压基本相同的电压; 并且其中在所述第二操作模式中，所述电路块接收的电压小于所述电压轨的电压阈值电压。