公开(公告)号：US20110013643A1

公开(公告)日：2011-01-20

申请号：US12890551

申请日：2010-09-24

Applicant: Brian Hang Wai Yang ,  Kai-Yeung (Sunny) Siu ,  Mizanur M. Rahman ,  Wei-Han Lien ,  Gaurav Singh

Inventor： Brian Hang Wai Yang ,  Kai-Yeung (Sunny) Siu ,  Mizanur M. Rahman ,  Wei-Han Lien ,  Gaurav Singh

IPC: H04L12/56

CPC classification number: H04L49/25 ,  H04L49/101 ,  H04L49/3027 ,  H04L49/3045

Abstract: The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements. Whereby, the arbiter circuit scans the matrix during a first epoch, issues the set of grant signals, allows the set of granted service requests to substantially complete, and if necessary, scans the matrix during subsequent epochs. The invention also relates to a crossbar switch controller including an arbitration pre-processor coupled to the input terminal and the matrix circuit, and configured to represent the set of service request signals in the form of a mapping matrix, and further configured to transform a first mapping position of the service request signal to a second mapping position based, in part, on a mapping algorithm. The invention also includes an arbitration post-processor coupled to the output terminal and the matrix circuit, and further configured to transform the second mapping position of the service request signal back to the first mapping position.

Abstract translation: 本发明涉及一种交叉开关控制器，其包括输入端子，该输入端子被配置为从包括一组分组的一组虚拟输出队列接收一组服务请求信号。 本发明还包括耦合到输入端并被配置为以矩阵的形式表示服务请求信号集合的矩阵电路，其中每个服务请求信号由行位置M和列位置N描述。本发明进一步 包括被配置为在历元期间接收所述一组分组的一部分的输出终端，所述仲裁器电路被配置为在所述时期期间迭代地扫描所述矩阵，并向所述虚拟输出队列发出所述一组授权信号以确定哪些服务请求被授权， 以及仲裁器控制器，被配置为使用非冲突矩阵元素的阵列启动仲裁器电路。 由此，仲裁器电路在第一纪元期间扫描矩阵，发出授权信号集合，允许一组授权的服务请求基本上完成，并且如果需要，在随后的时期期间扫描矩阵。 本发明还涉及一种交叉开关控制器，其包括耦合到输入端和矩阵电路的仲裁预处理器，并且被配置为以映射矩阵的形式表示该组服务请求信号，并且还被配置为将第一 部分地基于映射算法将服务请求信号的映射位置映射到第二映射位置。 本发明还包括耦合到输出端和矩阵电路的仲裁后处理器，还被配置为将服务请求信号的第二映射位置转换回第一映射位置。

公开(公告)号：US06622237B1

公开(公告)日：2003-09-16

申请号：US09476192

申请日：2000-01-03

Applicant: James B. Keller ,  Thomas S. Green ,  Wei-Han Lien ,  Ramsey W. Haddad ,  Keith R. Schakel

Inventor： James B. Keller ,  Thomas S. Green ,  Wei-Han Lien ,  Ramsey W. Haddad ,  Keith R. Schakel

IPC: G06F900

CPC classification number: G06F9/3834 ,  G06F9/3838

Abstract: A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor may be untrained (e.g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor as dependent upon a particular store and the dependency does not actually occur. In one implementation, the STLF predictor records at least a portion of the PC of a store which interferes with the load in a first table indexed by the load PC. A second table maintains a corresponding portion of the store PCs of recently dispatched stores, along with tags identifying the recently dispatched stores. In another implementation, the STLF predictor records a difference between the tags assigned to a load and a store which interferes with the load in a first table indexed by the load PC. The PC of the dispatching load is used to select a difference from the table, and the difference is added to the tag assigned to the load.

Abstract translation: 处理器使用存储来加载（STLF）预测器，其可以指示用于调度负载对存储的依赖性。 对于在先前执行期间干扰负载的执行的存储器，指示依赖性。 由于在存储器上指示依赖关系，所以在存储之前防止了负载的调度和/或执行。 响应于执行负载并存储和检测干扰，STLF预测器被训练用于特定负载和存储的信息。 此外，如果由STLF预测器指示负载依赖于特定存储并且实际上不发生依赖性，则STLF预测器可以是未经训练的（例如，针对特定负载的信息可以被删除）。 在一个实现中，STLF预测器在由负载PC索引的第一表中记录干扰负载的商店的PC的至少一部分。 第二个表维护最近派驻的商店的商店PC的相应部分，以及标识最近派发的商店的标签。 在另一实现中，STLF预测器记录分配给负载的标签与由负载PC索引的第一表中的负载干扰的存储器之间的差异。 调度负载的PC用于选择与表的差异，并将差值添加到分配给负载的标签。

公开(公告)号：US09158541B2

公开(公告)日：2015-10-13

申请号：US12938921

申请日：2010-11-03

Applicant: Wei-Han Lien

Inventor： Wei-Han Lien

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3012 ,  G06F9/30123

Abstract: A processor may include a physical register file and a register renamer. The register renamer may be organized into even and odd banks of entries, where each entry stores an identifier of a physical register. The register renamer may be indexed by a register number of an architected register, such that the renamer maps a particular architected register to a corresponding physical register. Individual entries of the renamer may correspond to architected register aliases of a given size. Renaming aliases that are larger than the given size may involve accessing multiple entries of the renamer, while renaming aliases that are smaller than the given size may involve accessing a single renamer entry.

Abstract translation: 处理器可以包括物理寄存器文件和寄存器重命名器。 寄存器重命名器可以被组织成偶数和奇数条目，其中每个条目存储物理寄存器的标识符。 寄存器重命名器可以由架构的寄存器的寄存器编号索引，使得重命名器将特定的架构寄存器映射到相应的物理寄存器。 重命名的个体条目可以对应于给定大小的架构的寄存器别名。 重命名大于给定大小的别名可能涉及访问重命名的多个条目，而重命名小于给定大小的别名可能涉及访问单个重命名条目。

公开(公告)号：US20070113060A1

公开(公告)日：2007-05-17

申请号：US11281832

申请日：2005-11-17

Applicant: Wei-Han Lien ,  Daniel Murray ,  Junji Sugisawa

Inventor： Wei-Han Lien ,  Daniel Murray ,  Junji Sugisawa

IPC: G06F7/38

CPC classification number: G06F9/3842 ,  G06F9/30094 ,  G06F9/384 ,  G06F9/3863

Abstract: In one embodiment, a processor comprises a plurality of storage locations, a decode circuit, and a status/control register (SCR). Each storage location is addressable as a speculative register and is configured to store result data generated during execution of an instruction operation and a value representing an update for the SCR. The value includes at least a first encoding that represents an update to a plurality of bits in the SCR, and a first number of bits in the plurality of bits is greater than a second number of bits in the first encoding. The decode circuit is coupled to receive the first encoding from a first storage location responsive to retirement of a first instruction operation assigned to use the first storage location as a destination, and is configured to decode the first encoding and generate the plurality of bits. The decode circuit is configured to update the SCR.

Abstract translation: 在一个实施例中，处理器包括多个存储位置，解码电路和状态/控制寄存器（SCR）。 每个存储位置可寻址为推测寄存器，并且被配置为存储在执行指令操作期间生成的结果数据和表示SCR的更新的值。 该值至少包括表示对SCR中的多个比特的更新的第一编码，并且多个比特中的第一比特数大于第一编码中的第二比特数。 解码电路被耦合以响应于分配给使用第一存储位置的目的地的第一指令操作的退出从第一存储位置接收第一编码，并且被配置为对第一编码进行解码并生成多个位。 解码电路被配置为更新SCR。

公开(公告)号：US20070050602A1

公开(公告)日：2007-03-01

申请号：US11214193

申请日：2005-08-29

Applicant: Wei-Han Lien ,  John Yong ,  Shyam Sundar ,  Rajat Goel

Inventor： Wei-Han Lien ,  John Yong ,  Shyam Sundar ,  Rajat Goel

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3861

Abstract: In one embodiment, a renamer comprises a plurality of storage locations and compare circuitry. Each storage location is assigned to a respective renameable resource and is configured to store an identifier corresponding to a youngest instruction operation that writes the respective renameable resource. Coupled to receive an input representing one or more retiring instruction identifiers corresponding to instruction operations that are being retired, the compare circuitry is configured to detect a match between at least a first identifier in a first storage location and one of the retiring identifiers. An encoded form of the identifiers is logically divided into a plurality of fields, and the input comprises a first plurality of bit vectors. Each of the first plurality of bit vectors corresponds to a respective field and includes a bit position for each possible value of the respective field.

Abstract translation: 在一个实施例中，重新映射器包括多个存储位置和比较电路。 每个存储位置被分配给相应的可重命名资源，并且被配置为存储对应于写入相应可重命名资源的最小指令操作的标识符。 耦合以接收表示与正在退休的指令操作相对应的一个或多个退休指令标识符的输入，所述比较电路被配置为检测第一存储位置中的至少第一标识符与退出标识符之一的匹配。 标识符的编码形式在逻辑上被划分为多个字段，并且输入包括第一多个比特向量。 第一多个位向量中的每一个对应于相应的场，并且包括相应场的每个可能值的比特位置。

公开(公告)号：US06694424B1

公开(公告)日：2004-02-17

申请号：US09476579

申请日：2000-01-03

Applicant: James B. Keller ,  Thomas S. Green ,  Wei-Han Lien ,  Ramsey W. Haddad

Inventor： James B. Keller ,  Thomas S. Green ,  Wei-Han Lien ,  Ramsey W. Haddad

IPC: G06F900

CPC classification number: G06F9/3855 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3859

Abstract: A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor may be untrained (e.g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor as dependent upon a particular store and the dependency does not actually occur. In one implementation, the STLF predictor records at least a portion of the PC of a store which interferes with the load in a first table indexed by the load PC. A second table maintains a corresponding portion of the store PCs of recently dispatched stores, along with tags identifying the recently dispatched stores. In another implementation, the STLF predictor records a difference between the tags assigned to a load and a store which interferes with the load in a first table indexed by the load PC. The PC of the dispatching load is used to select a difference from the table, and the difference is added to the tag assigned to the load.

Abstract translation: 处理器使用存储来加载（STLF）预测器，其可以指示用于调度负载对存储的依赖性。 对于在先前执行期间干扰负载的执行的存储器，指示依赖性。 由于在存储器上指示依赖关系，所以在存储之前防止了负载的调度和/或执行。 响应于执行负载并存储和检测干扰，STLF预测器被训练用于特定负载和存储的信息。 此外，如果由STLF预测器指示负载依赖于特定存储并且实际上不发生依赖性，则STLF预测器可以是未经训练的（例如，针对特定负载的信息可以被删除）。 在一个实现中，STLF预测器在由负载PC索引的第一表中记录干扰负载的商店的PC的至少一部分。 第二个表维护最近派驻的商店的商店PC的相应部分，以及标识最近派发的商店的标签。 在另一实现中，STLF预测器记录分配给负载的标签与由负载PC索引的第一表中的负载干扰的存储器之间的差异。 调度负载的PC用于选择与表的差异，并将差值添加到分配给负载的标签。

公开(公告)号：US20120110305A1

公开(公告)日：2012-05-03

申请号：US12938921

申请日：2010-11-03

Applicant: Wei-Han Lien

Inventor： Wei-Han Lien

IPC: G06F9/30

CPC classification number: G06F9/384 ,  G06F9/3012 ,  G06F9/30123

Abstract: A processor may include a physical register file and a register renamer. The register renamer may be organized into even and odd banks of entries, where each entry stores an identifier of a physical register. The register renamer may be indexed by a register number of an architected register, such that the renamer maps a particular architected register to a corresponding physical register. Individual entries of the renamer may correspond to architected register aliases of a given size. Renaming aliases that are larger than the given size may involve accessing multiple entries of the renamer, while renaming aliases that are smaller than the given size may involve accessing a single renamer entry.

Abstract translation: 处理器可以包括物理寄存器文件和寄存器重命名器。 寄存器重命名器可以被组织成偶数和奇数条目，其中每个条目存储物理寄存器的标识符。 寄存器重命名器可以由架构的寄存器的寄存器编号索引，使得重命名器将特定的架构寄存器映射到相应的物理寄存器。 重命名的个体条目可以对应于给定大小的架构的寄存器别名。 重命名大于给定大小的别名可能涉及访问重命名的多个条目，而重命名小于给定大小的别名可能涉及访问单个重命名条目。

公开(公告)号：US20120079249A1

公开(公告)日：2012-03-29

申请号：US12892438

申请日：2010-09-28

Applicant: Wei-Han Lien ,  Ian D. Kountanis ,  Shyam Sundar

Inventor： Wei-Han Lien ,  Ian D. Kountanis ,  Shyam Sundar

IPC: G06F9/30

CPC classification number: G06F9/3822 ,  G06F9/30145

Abstract: In an embodiment, a decode unit includes multiple decoders configured to decode different types of instructions. One or more of the decoders may be complex decoders, and the decode unit may disable the complex decoders if an instruction of the corresponding type is not being decoded. In an embodiment, the decode unit may disable the complex decoders by data-gating the instruction into the decoder. The decode unit may also include a control unit that is configured to detect instructions of the type decoded by the complex decoders, and to enable the complex decoders and redirect the fetching in response to the detection. The decode unit may also record an indication of the instruction (e.g. the program counter address (PC) of the instruction) to more rapidly detect the instruction and prevent a redirect in subsequent fetches.

Abstract translation: 在一个实施例中，解码单元包括被配置为解码不同类型的指令的多个解码器。 一个或多个解码器可以是复杂解码器，并且如果对应类型的指令未被解码，则解码单元可以禁用复数解码器。 在一个实施例中，解码单元可以通过将解码器的指令进行数据门控来禁用复数解码器。 解码单元还可以包括控制单元，其被配置为检测由复合解码器解码的类型的指令，并且使得复制解码器能够响应于检测而重定向该取出。 解码单元还可以记录指令的指示（例如，指令的程序计数器地址（PC）），以更快速地检测指令并防止后续读取中的重定向。

公开(公告)号：US07826477B2

公开(公告)日：2010-11-02

申请号：US12170269

申请日：2008-07-09

Applicant: Brian Hang Wal Yang ,  Kai-Yeung (Sunny) Siu ,  Mizanur M. Rahman ,  Wei-Han Lien ,  Gaurav Singh

Inventor： Brian Hang Wal Yang ,  Kai-Yeung (Sunny) Siu ,  Mizanur M. Rahman ,  Wei-Han Lien ,  Gaurav Singh

IPC: H04L12/54

CPC classification number: H04L49/25 ,  H04L49/101 ,  H04L49/3027 ,  H04L49/3045

Abstract: The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements.

Abstract translation: 本发明涉及一种交叉开关控制器，其包括输入端子，该输入端子被配置为从包括一组分组的一组虚拟输出队列接收一组服务请求信号。 本发明还包括耦合到输入端并被配置为以矩阵的形式表示服务请求信号集合的矩阵电路，其中每个服务请求信号由行位置M和列位置N描述。本发明进一步 包括被配置为在历元期间接收所述一组分组的一部分的输出终端，所述仲裁器电路被配置为在所述时期期间迭代地扫描所述矩阵，并向所述虚拟输出队列发出所述一组授权信号以确定哪些服务请求被授权， 以及仲裁器控制器，被配置为使用非冲突矩阵元素的阵列启动仲裁器电路。

公开(公告)号：US07426216B2

公开(公告)日：2008-09-16

申请号：US10302015

申请日：2002-11-21

Applicant: Brian Hang Wal Yang ,  Kai-Yeung (Sunny) Siu ,  Mizanur M. Rahman ,  Wei-Han Lien ,  Gaurav Singh

Inventor： Brian Hang Wal Yang ,  Kai-Yeung (Sunny) Siu ,  Mizanur M. Rahman ,  Wei-Han Lien ,  Gaurav Singh

IPC: H04L12/54

CPC classification number: H04L49/25 ,  H04L49/101 ,  H04L49/3027 ,  H04L49/3045

Abstract: The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. It also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. An output terminal is configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements. The Arbiter is configured to scan the matrix during a first epoch, issues the set of grant signals, allows the set of granted service requests to substantially complete, and if necessary, scans the matrix during subsequent epochs.

Abstract translation: 本发明涉及一种交叉开关控制器，其包括输入端子，该输入端子被配置为从包括一组分组的一组虚拟输出队列接收一组服务请求信号。 它还包括耦合到输入端并被配置为以矩阵的形式表示服务请求信号集合的矩阵电路，其中每个服务请求信号由行位置M和列位置N描述。输出端是 被配置为在历元期间接收该组分组的一部分，仲裁器电路被配置为在该时期期间迭代地扫描该矩阵，并向该虚拟输出队列发出一组授权信号以确定哪个服务请求被授予，以及一个仲裁器控制器 被配置为以不冲突的矩阵元素的阵列启动仲裁器电路。 仲裁器被配置为在第一纪元期间扫描矩阵，发出授权信号集合，允许一组授权的服务请求基本上完成，并且如果需要，在随后的时期期间扫描矩阵。