Drive chip and display panel
    11.
    发明授权

    公开(公告)号:US12211810B2

    公开(公告)日:2025-01-28

    申请号:US17613003

    申请日:2021-10-20

    Abstract: The present application discloses a drive chip and a display panel. The drive chip includes a first area and a second area. The drive chip includes a substrate and drive pins. The density of the pins located in the first area is lower than the density of the pins located in the second area. The pins located in the second area includes first drive pins and second drive pins. The distance between the substrate and a face of the first drive pins away from the substrate is greater than the distance between the substrate and a face of the second drive pins away from the substrate. The occurrence of poor electric conduction is avoided.

    Drive method for display panel
    12.
    发明授权

    公开(公告)号:US10789894B2

    公开(公告)日:2020-09-29

    申请号:US16332357

    申请日:2018-12-21

    Abstract: A drive method for a display panel is provided. A first multiplex signal, a second multiplex signal, a third multiplex signal, a fourth multiplex signal, a fifth multiplex signal, and a sixth multiplex signal sequentially generate the high level pulse in the predetermined order in each of the first row periods of the (2i−1)th multiplex period. In addition, the first multiplex signal, the second multiplex signal, the third multiplex signal, the fourth multiplex signal, the fifth multiplex signal, and the sixth multiplex signal sequentially generate the high level pulse in a reverse order to the predetermined order in each of the second row periods of the (2i)th multiplex period. As a result, mura within the display picture of the display panel is eliminated to improve the display quality.

    Drive method for display panel
    15.
    发明授权

    公开(公告)号:US10861367B2

    公开(公告)日:2020-12-08

    申请号:US16335249

    申请日:2018-12-19

    Abstract: According to a drive method for the display panel, m multiplex signals sequentially generate the high level pulse at the beginning of the (2i−1)th row period in a predetermined order. The high level pulse of the multiplex signal that is the last one to generate the high level pulse in the (2i−1)th row period continues until the end of the (2i−1)th row period. The m multiplex signals sequentially generate the high level pulse at the beginning of the (2i)th row period in a reverse order to the predetermined order. The high level pulse of the multiplex signal that is the last one to generate the high level pulse in the (2i)th row period continues until the end of the 2i row period. As a result, the number of times that the levels of the multiplex signals are changed in a frame period can be decreased to reduce the power consumption.

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