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公开(公告)号:US12211810B2
公开(公告)日:2025-01-28
申请号:US17613003
申请日:2021-10-20
Inventor: Shuya Dong , Haosen Ge , Yong Tian , Bo Liu
IPC: H01L23/00 , G02F1/1345 , H01L25/18 , H10K59/90
Abstract: The present application discloses a drive chip and a display panel. The drive chip includes a first area and a second area. The drive chip includes a substrate and drive pins. The density of the pins located in the first area is lower than the density of the pins located in the second area. The pins located in the second area includes first drive pins and second drive pins. The distance between the substrate and a face of the first drive pins away from the substrate is greater than the distance between the substrate and a face of the second drive pins away from the substrate. The occurrence of poor electric conduction is avoided.
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公开(公告)号:US10789894B2
公开(公告)日:2020-09-29
申请号:US16332357
申请日:2018-12-21
Inventor: Lihua Zheng , Mang Zhao , Yong Tian
IPC: G09G3/3266 , G09G3/36
Abstract: A drive method for a display panel is provided. A first multiplex signal, a second multiplex signal, a third multiplex signal, a fourth multiplex signal, a fifth multiplex signal, and a sixth multiplex signal sequentially generate the high level pulse in the predetermined order in each of the first row periods of the (2i−1)th multiplex period. In addition, the first multiplex signal, the second multiplex signal, the third multiplex signal, the fourth multiplex signal, the fifth multiplex signal, and the sixth multiplex signal sequentially generate the high level pulse in a reverse order to the predetermined order in each of the second row periods of the (2i)th multiplex period. As a result, mura within the display picture of the display panel is eliminated to improve the display quality.
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公开(公告)号:US10152922B2
公开(公告)日:2018-12-11
申请号:US14863610
申请日:2015-08-10
Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. , WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
Inventor: Juncheng Xiao , Mang Zhao , Yong Tian
IPC: G09G3/3266 , G09G3/36 , G09G3/3233 , H01L21/822 , H01L27/12
Abstract: The present invention provides a scan driving circuit utilized to drive cascading scan lines. The scan driving circuit comprises a pull-down control module, a pull-down module, a reset control module, a reset module, a lower transmission module, a first bootstrap capacitor, a constant low voltage source, and a constant high voltage source. By use of the deployment of the reset module, the scan driving circuit of the present invention improves the stability of the scan driving circuit and meanwhile, the structure of the whole scan driving circuit is simplified.
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公开(公告)号:US09786240B2
公开(公告)日:2017-10-10
申请号:US14779016
申请日:2015-08-10
Inventor: Mang Zhao , Yong Tian , Shijuan Yi
CPC classification number: G09G3/3677 , G09G3/20 , G09G2310/0267 , G09G2310/0286 , G09G2330/021 , G11C19/00 , G11C19/287
Abstract: A scan driving circuit is provided. The scan driving circuit for driving cascaded scan lines includes a scan driving circuit, a latch module, a driving-signal generation module, an output control module, a high gate voltage source, and a low level gate voltage. The scan driving circuit of the present invention conducts a driving operation for the latch module by a first cascade signal and a second cascade signal, so that a clock signal is not required to be processed with a phase inversion, and thereby the scan driving circuit has less overall power consumption.
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公开(公告)号:US10861367B2
公开(公告)日:2020-12-08
申请号:US16335249
申请日:2018-12-19
Inventor: Lihua Zheng , Mang Zhao , Yong Tian
Abstract: According to a drive method for the display panel, m multiplex signals sequentially generate the high level pulse at the beginning of the (2i−1)th row period in a predetermined order. The high level pulse of the multiplex signal that is the last one to generate the high level pulse in the (2i−1)th row period continues until the end of the (2i−1)th row period. The m multiplex signals sequentially generate the high level pulse at the beginning of the (2i)th row period in a reverse order to the predetermined order. The high level pulse of the multiplex signal that is the last one to generate the high level pulse in the (2i)th row period continues until the end of the 2i row period. As a result, the number of times that the levels of the multiplex signals are changed in a frame period can be decreased to reduce the power consumption.
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16.
公开(公告)号:US10078991B2
公开(公告)日:2018-09-18
申请号:US15310100
申请日:2016-08-26
IPC: G09G3/36
CPC classification number: G09G3/3648 , G09G2300/0819 , G09G2310/0251 , G09G2320/0242 , G09G2320/0247
Abstract: The present invention provides a liquid crystal driving circuit for providing power to the pixel units of a liquid crystal display device. The present invention further provides the liquid crystal display device, which comprises pixel units and the liquid crystal driving circuit.
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