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公开(公告)号：US09818357B2
公开(公告)日：2017-11-14
申请号：US14787299
申请日：2015-08-28
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng Xiao , Mang Zhao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2300/0809 , G09G2310/0267 , G09G2310/0286 , G11C19/28
Abstract: A GOA circuit and an LCD are disclosed. The GOA circuit includes multiple cascaded GOA units and a control module. Each of the multiple cascaded GOA units is used for charging a corresponding horizontal scanning line in a display area through driving of a first stage-transferring clock, a second stage-transferring clock, a first control clock and a second control clock. The control module is used to control the gate driving signals to be reset to the first voltage level, that is an ineffective voltage level, after the GOA circuit finishes a charging for all of the horizontal scanning lines simultaneously through the starting pulse signal such that a redundant pulse signal generated on the horizontal scanning lines before the gate driving signal of the first stage GOA unit is outputted is avoided in order to ensure a normal operation of the GOA circuit.
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公开(公告)号：US09761194B2
公开(公告)日：2017-09-12
申请号：US14786537
申请日：2015-10-12
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Mang Zhao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3696 , G09G2300/0408 , G09G2300/0871 , G09G2310/0286 , G09G2310/08
Abstract: The present invention provides a CMOS GOA circuit. The first NOR gate (Y1) and the second NOR gate (Y2) are located in the input control module (1). The two input ends of the first NOR gate (Y1) respectively receives the stage transfer signal (Q(N−1)) of the GOA unit circuit of the former stage and the global signal (Gas), and the two input ends of the second NOR gate (Y2) respectively receives the first clock signal (CK1) and the global signal (Gas). When the global signal (Gas) is high voltage level, the all the scan driving signals (G(N)) of the respective stages are controlled to be raised up to high voltage levels at the same time, and meanwhile, both the first NOR gate (Y1) and the second NOR gate (Y2) are controlled to output low voltage levels to control the inverted stage transfer signal (XQ(N)) to be high voltage level.
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公开(公告)号：US12067925B2
公开(公告)日：2024-08-20
申请号：US18149027
申请日：2022-12-30
Inventor： Liu Yang , Qiang Gong , Mang Zhao
IPC: G09G3/20
CPC classification number: G09G3/2074 , G09G2300/0452 , G09G2310/0202 , G09G2310/0297 , G09G2310/08 , G09G2320/0626 , G09G2320/0666
Abstract: Provided are a display panel and an electronic terminal, including pixel units arranged along row and column directions. The pixel unit includes sub-pixels of different colors arranged along the row direction. In a first mode, two adjacent groups of pixel units are simultaneously turned on, and the sub-pixels of a same color in two adjacent columns of pixel units display a same gray scale. In a second mode, a plurality of rows of pixel units are turned on sequentially, and each sub-pixel in a plurality of columns of pixel units displays a corresponding gray scale. The refresh rate of the first mode is greater than that of the second mode, and the resolution of the first mode is smaller than that of the second mode. This shortens the time required for all rows of pixel units to be turned on, thereby increasing the refresh rate.
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公开(公告)号：US10861368B2
公开(公告)日：2020-12-08
申请号：US16492137
申请日：2019-05-07
Inventor： Lihua Zheng , Mang Zhao
IPC: G09G3/20
Abstract: A driving method for a display panel is through making the first demultiplexing signal, the second demultiplexing signal, the third demultiplexing signal, the fourth demultiplexing signal, the fifth demultiplexing signal and the sixth demultiplexing signal according to the first sequence generate the high-level pulse in the first image frame, and through making the first demultiplexing signal, the second demultiplexing signal, the third demultiplexing signal, the fourth demultiplexing signal, the fifth demultiplexing signal and the sixth demultiplexing signal according to the second sequence different from the first sequence generate the high-level pulse in the second image frame, thereby by adding the effect of the two image frames to eliminate stripes on the images displayed by the display panel to improve the display effect.
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公开(公告)号：US10861367B2
公开(公告)日：2020-12-08
申请号：US16335249
申请日：2018-12-19
Inventor： Lihua Zheng , Mang Zhao , Yong Tian
Abstract: According to a drive method for the display panel, m multiplex signals sequentially generate the high level pulse at the beginning of the (2i−1)th row period in a predetermined order. The high level pulse of the multiplex signal that is the last one to generate the high level pulse in the (2i−1)th row period continues until the end of the (2i−1)th row period. The m multiplex signals sequentially generate the high level pulse at the beginning of the (2i)th row period in a reverse order to the predetermined order. The high level pulse of the multiplex signal that is the last one to generate the high level pulse in the (2i)th row period continues until the end of the 2i row period. As a result, the number of times that the levels of the multiplex signals are changed in a frame period can be decreased to reduce the power consumption.
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Patent Agency Ranking
公开(公告)号：US10417977B2
公开(公告)日：2019-09-17
申请号：US15552277
申请日：2017-05-26
Inventor： Mang Zhao
IPC: G06F3/038 , G09G3/36 , G09G5/00 , G02F1/1368 , G02F1/1362 , G09G3/3266
Abstract: A scan driving circuit, and an array substrate and a display panel having the scan driving circuit are disclosed. The scan driving circuit includes a plurality of cascaded scan driving units. Each scan driving unit includes an input unit and an output unit. The input unit receives the activation trigger signal, transmits to the output unit and controls the output units in a scanning state. The scan driving unit includes a scan signal modulation unit having at least two transistors. The transistors output a clock modulation signal according to a plurality of clock signals. The clock modulation signal includes at least two first voltages separated with predetermined duration. The output unit outputs scan driving signal from the scan signal output end according to the clock modulation signal. The scan signal includes two sub-scan signals to control pixel unit to receive image data within a scan cycle.
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公开(公告)号：US20180301107A1
公开(公告)日：2018-10-18
申请号：US15021461
申请日：2016-02-26
IPC: G09G3/36 , H03K17/687
CPC classification number: G09G3/3696 , G02F1/13 , G09G3/36 , G09G3/3677 , G09G2300/0866 , G09G2310/0289 , G09G2320/0214 , H03K17/6871
Abstract: A GOA circuit includes GOA circuit units. Each GOA circuit has a holding module A first transistor and a second transistor in the holding module holds the voltage imposed on the first control node to be at high voltage level. Also, the transistors form a direct current passage between the first control node and a first fixed voltage at high voltage level so the voltage imposed on the first control node is not lowered due to electricity leakage. The GOA circuit unit can resolve the problem of easy leakage of electricity. When the scanning signals are output by the GOA circuit unit, the stability is highly ensured.
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公开(公告)号：US20180151139A1
公开(公告)日：2018-05-31
申请号：US15119385
申请日：2016-05-25
Inventor： Shijuan Yi , Mang Zhao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/36 , G09G2310/0286 , G09G2310/0291 , G09G2310/062 , G09G2320/0223 , G09G2330/021
Abstract: The CMOS GOA circuit of reducing clock signal loading comprises the input control module (1), the latch module (2), the reset module (3), the signal process module (4) and the output buffer module (5); in the input control module (1), the clock signal (CK(M)) merely needs to control the second N type thin film transistor and the fifth N type thin film transistor (T2, T5), and the amount of the thin film transistors driven by the clock signal can be decreased to reduce the clock signal loading, and to lower the RC delay and the power consumption of the clock signal; the latch module (2) utilizes the inverted scan drive signal (XGate(N−2)) of the two former N-2th stage GOA unit to be the input control signal of the stage transfer signal Q(N) to solve the competition problem occurs as the stage transfer signal (Q(N)) is inputted.
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公开(公告)号：US09972273B2
公开(公告)日：2018-05-15
申请号：US14891646
申请日：2015-10-21
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng Xiao , Mang Zhao
IPC: G09G3/36 , G02F1/1362 , G02F1/1368 , G02F1/1335
CPC classification number: G09G3/3696 , G02F1/133514 , G02F1/136204 , G02F1/1368 , G02F2202/22 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/04 , G11C19/184
Abstract: The invention disclosure a GOA circuit and a liquid crystal display. The GOA circuit including an electrical potential pull-down controlling circuit and a plurality of GOA sub circuits in cascade connection, the electrical potential pull-down controlling circuit comprising a first voltage limited transistor, a second filter transistor and a third transistor. The first voltage limited transistor, and the second filter transistor a reconnected in series and between the output terminal of the initial scanning signal, STV signal and the control terminal of the third transistor, the control terminal of the first voltage limited transistor and the first terminal of the third transistor is connected to the first power terminal and the second terminal of the third transistor is connected to the GOA sub circuit. By this design, the damage from the large static electricity to the GOA sub circuit can be avoided.
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公开(公告)号：US09847069B2
公开(公告)日：2017-12-19
申请号：US14917571
申请日：2016-01-29
Inventor： Mang Zhao
CPC classification number: G09G3/3677 , G09G3/36 , G09G2300/0408 , G09G2310/0286 , G09G2310/0289 , G09G2310/08
Abstract: The present invention provides a GOA circuit and a liquid crystal display device. The GOA circuit adds the stage transfer unit (900) and the stage transfer pull-down unit (800) and modifying the global control auxiliary unit (1000) to use the stage transfer end (ST(N)) of the stage transfer unit (900) to output the signal which is different from the scan driving signal to be the stage transfer signal and to use the global control auxiliary unit (1000) to stable the voltage level of the stage transfer end (ST(N)) in the period that the output ends (G(N)) of all the GOA units output the scan driving signal at the same time, the signal outputted by the stage transfer end (ST(N)) is opposite to the voltage level of the scan driving signal.
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