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公开(公告)号：US20180034462A1
公开(公告)日：2018-02-01
申请号：US15023380
申请日：2016-02-25
Inventor： Mang ZHAO
IPC: H03K17/687 , G09G3/36
CPC classification number: H03K17/6872 , G09G3/3677 , G09G2310/0286
Abstract: A gate driving circuit and a liquid crystal display are disclosed. The gate driving circuit includes: an input and latch circuit, a signal processing circuit electrically connected with the input and latch circuit and an output buffering circuit electrically connected with the signal processing circuit. Wherein, the input and latch circuit or the signal processing circuit includes two switch modules which are disposed in parallel. Each switch module includes two switching tubes disposed in series, control terminals of the two switching tubes of one of the two switch modules are crosswise connected with control terminals of the two switching tubes of the other of the two switch modules. The present invention through disposing two switch modules and crosswise connecting the control terminals of the switching tubes, the stress degrees applied on the two switching transistors are the same so as to greatly increase the stability of the circuit operation.
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公开(公告)号：US20170323605A1
公开(公告)日：2017-11-09
申请号：US14783863
申请日：2015-08-27
Inventor： Juncheng XIAO , Mang ZHAO
CPC classification number: G09G3/3614 , G09G3/20 , G09G3/30 , G09G3/36 , G09G3/3677 , G09G2310/0232 , G09G2310/0267 , G09G2310/0286 , G09G2330/021 , G11C19/28
Abstract: A scan driving circuit is provided for driving scan line in cascade, including a pull-down controlling module, a pull-down module, a reset-controlling module, a resetting module, a downward-transferring module, a first bootstrap capacitor, a constant low voltage level source, and a constant high voltage level source. By disposing the resetting module, the scan driving circuit of the present invention raises the reliability of the scan driving circuit and simplifies the entire structure of the scan driving circuit.
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公开(公告)号：US20170160607A1
公开(公告)日：2017-06-08
申请号：US14888971
申请日：2015-07-31
Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd. , Wuhan China Star Optoelectronics Technology Co. Ltd.
Inventor： Mang ZHAO , Yong TIAN , Caiqin CHEN
IPC: G02F1/1362 , H02H9/04 , H01L27/12 , H01L27/02 , G09G3/36 , G02F1/1368
CPC classification number: G02F1/136204 , G02F1/1362 , G02F1/136286 , G02F1/1368 , G02F2201/503 , G09G3/20 , G09G3/3677 , G09G2300/0408 , G09G2330/04 , G09G2330/06 , H01L27/0255 , H01L27/0292 , H01L27/0296 , H01L27/1244 , H02H9/046
Abstract: The present disclosure relates to an array substrate, a display panel and a display device. The array substrate includes GND wirings and GOA areas. The GND wirings are configured at outer sides of the GOA areas, and the GOA area includes a variety of GOA signal lines and N-th stage GOA circuits electrically connected by the GOA signal lines. A first ESD protection circuit is configured in a middle area between the 1-th stage GOA circuit and the N-th stage GOA circuit to discharge abnormal electrical charges of the GOA signal lines within the middle area. With such configuration, better ESD protection capability is provided between the GOA signal lines.
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公开(公告)号：US20170140728A1
公开(公告)日：2017-05-18
申请号：US14905967
申请日：2015-12-23
IPC: G09G3/36 , G02F1/1345 , G02F1/1368
CPC classification number: G09G3/3677 , G02F1/13454 , G02F1/1368 , G09G2300/0819 , G09G2310/0251 , G09G2310/0286 , G09G2310/08 , G09G2330/021
Abstract: A GOA circuit includes GOA circuit units. When scan signal outputted by a previous stage GOA circuit unit and a next stage GOA circuit unit are at a low level, a fifth transistor controlled by the scan signal of previous stage GOA circuit unit and a sixth transistor controlled by the scan signal of a next stage GOA circuit unit turn on, so that the current stage GOA circuit unit starts to operate, and voltage of a control node becomes the same as the first constant voltage. When a third clock signal is triggered, the scan signal of the previous stage GOA circuit unit is charged from the low level, which was maintained previously, to the first constant voltage. Therefore, scan signal of GOA circuit unit will not affect the normal stage transmission of other GOA circuit units, and mitigate the problem of outputting redundant scan signal pulse.
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公开(公告)号：US20170005642A1
公开(公告)日：2017-01-05
申请号：US14783100
申请日：2015-08-10
Inventor： Mang ZHAO , Yong TIAN , Gui CHEN , Caiqin CHEN , Xin ZHANG
CPC classification number: H03K3/012 , G09G3/3677 , G09G2300/0408 , G09G2300/0814 , G09G2310/0202 , G09G2310/0289
Abstract: A scan driving circuit configured for driving cascaded scan lines is provided, which includes an input control module, a latch module, a driving-signal generation module, an output control module, a constant high voltage source and a constant low voltage source. The scan driving circuit of the present invention drives the input control module through cascade signals of a preceding stage and cascade signals of a succeeding stage, so as to reduce interference and the driving power consumption of the scan driving circuit.
Abstract translation: 提供了一种用于驱动级联扫描线的扫描驱动电路，其包括输入控制模块，锁存模块，驱动信号生成模块，输出控制模块，恒定高压源和恒定低电压源。 本发明的扫描驱动电路通过前级级联信号和后级级联信号来驱动输入控制模块，以减少扫描驱动电路的干扰和驱动功耗。
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Patent Agency Ranking
公开(公告)号：US20210264868A1
公开(公告)日：2021-08-26
申请号：US16966034
申请日：2020-04-03
Inventor： Mang ZHAO
IPC: G09G3/36
Abstract: A gate driver on array (GOA) device and a display panel are proposed. In the present application, by adding a twenty-first transistor and a first control clock terminal electrically connected to the twenty-first transistor in a forward-reverse scan module to control potentials of a first node and a third node, a leakage of the first node during operation can be reduced, thereby improving reliability of the GOA device.
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公开(公告)号：US20200258437A1
公开(公告)日：2020-08-13
申请号：US16611225
申请日：2019-08-15
Inventor： Mang ZHAO
IPC: G09G3/20
Abstract: A GOA circuit and a display panel. By using a first control clock and a third control clock in a forward and reverse scanning module to control a first node, the GOA circuit is able to avoid leakage of the first node during operation and improve the reliability of GOA circuit.
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公开(公告)号：US20190385554A1
公开(公告)日：2019-12-19
申请号：US15735924
申请日：2017-10-21
Inventor： Mang ZHAO
IPC: G09G3/36
Abstract: The present disclosure provides a scan-driving circuit and a display device. The scan-driving circuit includes a plurality of series-connecting scan-driving units including an input circuit generating a pull-up control signal and a pull-down control signal; a latch circuit pulling up or pulling down a pull-up control signal point; a processing circuit generating a current scan-driving signal, a cache circuit driving an output of a current scan-driving signal, and a reset circuit clearing the pull-up control signal point. Therefore, it improves driving flexibility and reduces driving power consumption of the display device, and is beneficial to narrow bezel design.
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公开(公告)号：US20180330678A1
公开(公告)日：2018-11-15
申请号：US15552277
申请日：2017-05-26
Inventor： Mang ZHAO
IPC: G09G3/36
CPC classification number: G09G3/3607 , G02F1/136286 , G02F1/1368 , G09G3/3266 , G09G3/3677 , G09G2300/0426 , G09G2310/0286 , G09G2320/0242
Abstract: A scan driving circuit, and an array substrate and a display panel having the scan driving circuit are disclosed. The scan driving circuit includes a plurality of cascaded scan driving units. Each scan driving unit includes an input unit and an output unit. The input unit receives the activation trigger signal, transmits to the output unit and controls the output units in a scanning state. The scan driving unit includes a scan signal modulation unit having at least two transistors. The transistors output a clock modulation signal according to a plurality of clock signals. The clock modulation signal includes at least two first voltages separated with predetermined duration. The output unit outputs scan driving signal from the scan signal output end according to the clock modulation signal. The scan signal includes two sub-scan signals to control pixel unit to receive image data within a scan cycle.
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20.发明申请公开(公告)号：US20180061346A1
公开(公告)日：2018-03-01
申请号：US14916343
申请日：2016-02-24
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2310/0243 , G09G2310/0286 , G09G2310/0289 , G09G2310/08
Abstract: A gate driving circuit disposed on an array substrate and an LCD using the same are described. The gate driving circuit on the array substrate comprises a plurality of sequentially connected gate driving units. The gate driving circuit unit comprises an input module, a reset module, a latch module and a signal processing module. The signal processing module receives the current inverse stage-transmitting signal XQ(N), the low voltage signal, a second clock signal and a third clock signal to control on/off statuses of two transistors by the current stage-transmitting signal Q(N) so that the two transistors forms Nth gate signal G(N) and gate signal (N+1)th based on the second clock signal and the third clock signal. The present invention utilizes less clock signals and transistors, which is favorable to the narrower LCD's frame design and solves the problem of manufacturing process restriction of the LCD panel.
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