公开(公告)号：US06792516B2

公开(公告)日：2004-09-14

申请号：US10033440

申请日：2001-12-28

Applicant: Josh B. Mastronarde ,  Aditya Sreenivas ,  Thomas A. Piazza

Inventor： Josh B. Mastronarde ,  Aditya Sreenivas ,  Thomas A. Piazza

IPC: G06F1200

CPC classification number: G06F13/161 ,  G06F13/18

Abstract: Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

Abstract translation: 本发明的实施例提供了一种用于将芯片组和图形业务引导到系统存储器的存储器仲裁器。 页面一致性和优先级用于优化内存带宽利用率，并保证等时显示请求的延迟。 仲裁器还包含一种防止CPU请求饥饿较低优先级请求的机制。 因此，存储器仲裁器提供了一种简单易于验证的架构，防止CPU不利地挨饿低优先级代理，并利用宽限期和存储器页面检测来优化仲裁交换机，从而增加内存带宽利用率。

公开(公告)号：US06538650B1

公开(公告)日：2003-03-25

申请号：US09480833

申请日：2000-01-10

Applicant: Surti B. Prasoonkumar ,  Aditya Sreenivas

Inventor： Surti B. Prasoonkumar ,  Aditya Sreenivas

IPC: G06T1700

CPC classification number: G06T15/005 ,  G06F12/1027 ,  G06F2212/654

Abstract: A method and apparatus for efficient translation lookaside buffer (“TLB”) management of three-dimensional surfaces is disclosed. A three-dimensional surface is represented as a square pixel surface. The square-surface representation is stored in a single entry of the TLB.

Abstract translation: 公开了一种用于三维表面的有效翻译后备缓冲（“TLB”）管理的方法和装置。 三维表面被表示为正方形像素表面。 正方形表示形式存储在TLB的单个条目中。

公开(公告)号：US07173627B2

公开(公告)日：2007-02-06

申请号：US09895777

申请日：2001-06-29

Applicant: Peter L. Doyle ,  Aditya Sreenivas

Inventor： Peter L. Doyle ,  Aditya Sreenivas

IPC: G06F15/00 ,  G06F9/46

CPC classification number: G06F9/463

Abstract: A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A graphics context manager stores in a first memory area and restores from the first memory area information describing a first rendering context associated with a first independent image. The graphics context manager stores in a second memory area and restores from the second memory area information describing a second rendering context associated with a second independent image.

Abstract translation: 一种同时呈现独立图像以在一个或多个显示设备上显示的方法，装置和系统。 在一个实施例中，图形呈现引擎同时呈现独立图像以在多个显示设备上显示。 图形上下文管理器存储在第一存储器区域中，并且从第一存储器区域恢复描述与第一独立图像相关联的第一渲染上下文的信息。 图形上下文管理器存储在第二存储器区域中，并且从第二存储器区域恢复描述与第二独立图像相关联的第二渲染上下文的信息。

公开(公告)号：US07103730B2

公开(公告)日：2006-09-05

申请号：US10119864

申请日：2002-04-09

Applicant: Alankar Saxena ,  Aditya Sreenivas

Inventor： Alankar Saxena ,  Aditya Sreenivas

IPC: G06F12/00 ,  G06F1/32

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F12/0215 ,  G06F12/123 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: A method, system, and apparatus to reduce power consumption of a memory by actively asserting the CKE pin based at least in part on a LRU status of the rows in an active mode.

Abstract translation: 至少部分地基于活动模式中的行的LRU状态来主动地断言CKE引脚来减少存储器的功耗的方法，系统和装置。

公开(公告)号：US07035984B2

公开(公告)日：2006-04-25

申请号：US10038941

申请日：2001-12-31

Applicant: Josh B. Mastronarde ,  Aditya Sreenivas ,  Thomas A. Piazza

Inventor： Josh B. Mastronarde ,  Aditya Sreenivas ,  Thomas A. Piazza

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F13/1642

Abstract: Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

公开(公告)号：US06999091B2

公开(公告)日：2006-02-14

申请号：US10033439

申请日：2001-12-28

Applicant: Alankar Saxena ,  Aditya Sreenivas ,  Tom A. Piazza

Inventor： Alankar Saxena ,  Aditya Sreenivas ,  Tom A. Piazza

IPC: G06F12/02

CPC classification number: G09G5/39 ,  G09G2360/122 ,  G09G2360/125 ,  H04N19/423 ,  H04N19/61

Abstract: Embodiments of the present invention provide a method and apparatus for optimally mapping a tiled memory surface to two memory channels, operating in an interleaved fashion, maximizing the memory efficiency of the two channels, while maintaining the desired access granularity. In particular, an incoming request address is used to generate memory addresses for memory channels based on tile and request parameters. The memory controller stores the set of tiled data in the memory in a format such that selected sets of tiled data are stored in alternating channels of memory, such that data blocks are accessible at the same time, as opposed to sequentially. Thus if the memory controller received a block of data from a source, such as a graphics engine, the memory controller would store portions of the block of data within a single tile in the memory, partitioned such that it is retrievable via alternate channels of memory at the same time.

Abstract translation: 本发明的实施例提供了一种用于将平铺的存储器表面最佳地映射到两个存储器通道的方法和装置，以交错的方式操作，使两个通道的存储器效率最大化，同时保持期望的访问粒度。 特别地，输入请求地址用于基于瓦片和请求参数来生成用于存储器通道的存储器地址。 存储器控制器以这样的格式将该组平铺数据存储在存储器中，使得所选择的拼接数据集合被存储在存储器的交替通道中，使得数据块可以同时访问，而不是依次访问。 因此，如果存储器控制器从诸如图形引擎的源接收到数据块，则存储器控制器将存储器中的单个存储器中的数据块的部分存储在存储器中，从而被分割，使得其可经由存储器的备用通道 与此同时。

公开(公告)号：US20050283602A1

公开(公告)日：2005-12-22

申请号：US10873803

申请日：2004-06-21

Applicant: Balaji Vembu ,  Clifford Hall ,  Aditya Sreenivas

Inventor： Balaji Vembu ,  Clifford Hall ,  Aditya Sreenivas

IPC: G06F12/10 ,  G06F12/14 ,  G06F21/00 ,  H04L9/00

CPC classification number: G06F21/53 ,  G06F12/1036 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/145

Abstract: A method and apparatus for protected execution of graphics are described. In one embodiment, the method includes the formation of a translation table for a trusted application. In one embodiment, the translation table is formed according to one or more protected pages assigned to the trusted application in response to a protected page request from the trusted application. During execution of the trusted application, a virtual address space of the trusted application is translated to the one or more protected pages assigned to the trusted application. In one embodiment, the translation is performed according to the translation table assigned to the trusted application. Accordingly, by assigning a unique translation table to each trusted application, the various trusted applications may execute within the platform without generating an access into another application's physical address space. Other embodiments are described and claimed.

Abstract translation: 描述用于保护执行图形的方法和装置。 在一个实施例中，该方法包括形成可信应用的转换表。 在一个实施例中，响应于受信任应用的受保护的页面请求，根据分配给受信任应用的一个或多个受保护页形成翻译表。 在可信应用的执行期间，可信应用的虚拟地址空间被转换为分配给可信应用的一个或多个受保护的页面。 在一个实施例中，根据分配给可信应用的转换表来执行翻译。 因此，通过为每个可信应用分配唯一的转换表，各种可信应用可以在平台内执行，而不产生对另一个应用的物理地址空间的访问。 描述和要求保护其他实施例。

公开(公告)号：US20050195202A1

公开(公告)日：2005-09-08

申请号：US10796686

申请日：2004-03-08

Applicant: David Freker ,  Aditya Sreenivas ,  Zohar Bogin ,  Anoop Mukker ,  Tuong Trieu

Inventor： David Freker ,  Aditya Sreenivas ,  Zohar Bogin ,  Anoop Mukker ,  Tuong Trieu

IPC: G06F12/00 ,  G06F12/14 ,  G06F13/00

CPC classification number: G06F13/1684

Abstract: Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

Abstract translation: 本发明的实施例涉及使用双通道存储器件的第一通道访问第一对相邻数据块; 并且使用所述存储器件的第二通道同时访问第二对相邻数据块，所述第二对与所述第一对间隔开预定间隔。

公开(公告)号：US06724389B1

公开(公告)日：2004-04-20

申请号：US09823107

申请日：2001-03-30

Applicant: Adam H. Wilen ,  Marcus Grindstaff ,  Aditya Sreenivas

Inventor： Adam H. Wilen ,  Marcus Grindstaff ,  Aditya Sreenivas

IPC: G06F1314

CPC classification number: G06F3/14

Abstract: The present invention is a method and apparatus to map first graphics pins into second graphics pins. A first plurality of data and command pins corresponding to data and command signals in a first graphics mode is mapped into a second plurality of data and command pins corresponding to data and command signals in a second graphics mode. The first and second graphics modes are supported by a first chipset. The second graphics mode is supported by a second chipset. A detector pin strappable to a logic level to indicate an external graphics card is used in the first graphics mode is mapped into a first pin corresponding to a first signal of the second graphics mode. The first signal is ignored by the second chipset during initialization.

Abstract translation: 本发明是将第一图形引脚映射到第二图形引脚的方法和装置。 与第一图形模式中的数据和命令信号相对应的第一多个数据和命令引脚被映射到与第二图形模式中的数据和命令信号相对应的第二多个数据和命令引脚。 第一和第二图形模式由第一芯片组支持。 第二个图形模式由第二个芯片组支持。 在第一图形模式中使用被封装成逻辑电平以指示外部图形卡的检测器引脚被映射到对应于第二图形模式的第一信号的第一引脚。 第一个信号在初始化期间被第二个芯片组忽略。

公开(公告)号：US06628294B1

公开(公告)日：2003-09-30

申请号：US09476983

申请日：1999-12-31

Applicant: Jonathan B. Sadowsky ,  Aditya Sreenivas

Inventor： Jonathan B. Sadowsky ,  Aditya Sreenivas

IPC: G06F1210

CPC classification number: G06F12/1027 ,  G06F2212/654

Abstract: An embodiment of the invention is directed to a method including fetching address translations for a current group of scanlines of image data and prefetching address translations for a next group of scanlines of image data. The prefetching occurs while the current group of scanlines of image data is being rendered on a display. The current group of scanlines and the next group of scanlines may be the same size such that determining address translations for the next group of scanlines terminates at or before the time the current group of scanlines have been rendered on the display. A translation look aside buffer (TLB) controller may be used to implement the method. In a particular embodiment of the invention, a first buffer and a second buffer are used such that when one stores address translations for the current group of scanlines of image data, the other stores address translations for the next group of scanlines of image data.

Abstract translation: 本发明的一个实施例涉及一种方法，包括获取图像数据的当前扫描线组的地址转换以及图像数据的下一组扫描线的预取地址转换。 当图像数据的当前扫描线组在显示器上呈现时，发生预取。 当前组的扫描线和下一组扫描线可以具有相同的尺寸，使得为下一组扫描线确定地址转换在当前扫描线组在显示器上呈现之前或之前终止。 翻译后备缓冲区（TLB）控制器可用于实现该方法。 在本发明的特定实施例中，使用第一缓冲器和第二缓冲器，使得当存储图像数据的当前扫描线组的地址转换时，另一个存储针对图像数据的下一组扫描线的地址转换。