公开(公告)号：US20070045861A1

公开(公告)日：2007-03-01

申请号：US11591704

申请日：2006-11-02

申请人： Koichi Ohto ,  Tatsuya Usami ,  Noboru Morita ,  Sadayuki Ohnishi ,  Koji Arita ,  Ryohei Kitao ,  Yoichi Sasaki

发明人： Koichi Ohto ,  Tatsuya Usami ,  Noboru Morita ,  Sadayuki Ohnishi ,  Koji Arita ,  Ryohei Kitao ,  Yoichi Sasaki

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor substrate, and a multi-layered wiring arrangement provided thereon. The multi-layered wring arrangement includes at least one insulating layer structure having a metal wiring pattern formed therein. The insulating layer structure includes a first SiOCH layer, a second SiOCH layer formed on the first SiOCH layer, and a silicon dioxide (SiO2) layer formed on the second SiOCH layer. The second SiOCH layer features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer, and an oxygen (O) density higher than that of the first SiOCH layer.

摘要翻译： 半导体器件具有半导体衬底和设置在其上的多层布线装置。 多层绞合装置包括其中形成有金属布线图案的至少一个绝缘层结构。 绝缘层结构包括第一SiOCH层，形成在第一SiOCH层上的第二SiOCH层和形成在第二SiOCH层上的二氧化硅（SiO 2）层。 第二SiOCH层的碳（C）密度低于第一SiOCH层的碳（C）密度，氢（H）密度低于第一SiOCH层的密度，氧（O）密度高于第一SiOCH层 。

公开(公告)号：US20060276029A1

公开(公告)日：2006-12-07

申请号：US11503972

申请日：2006-08-15

申请人： Tatsuya Usami ,  Takashi Ishigami ,  Tetsuya Kurokawa ,  Noriaki Oda

发明人： Tatsuya Usami ,  Takashi Ishigami ,  Tetsuya Kurokawa ,  Noriaki Oda

IPC分类号： H01L21/4763

CPC分类号： H01L23/53295 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu film 209 is formed in multilayer films comprising a L-Ox™ film 203 and a SiO2 film 204. Since the L-Ox™ film 203 comprises ladder-shaped siloxane hydride structure, the film thickness and the film characteristics are stable, and thus changes in the film quality is scarcely occurred during the manufacturing process.

摘要翻译： 本发明降低了层间绝缘膜的有效介电常数，同时抑制了由吸湿引起的半导体器件的可靠性的降低。 包括Cu膜209的铜互连形成在包括L-Ox TM膜203和SiO 2膜204的多层膜中。由于L-Ox TM膜203包括梯形 - 形成硅氧烷氢化物结构，膜厚度和膜特性是稳定的，因此在制造过程中几乎不发生膜质量的变化。

公开(公告)号：US20050124168A1

公开(公告)日：2005-06-09

申请号：US10969429

申请日：2004-10-21

申请人： Seiji Nagahara ,  Kazutoshi Shiba ,  Nobuaki Hamanaka ,  Tatsuya Usami ,  Takashi Yokoyama

发明人： Seiji Nagahara ,  Kazutoshi Shiba ,  Nobuaki Hamanaka ,  Tatsuya Usami ,  Takashi Yokoyama

IPC分类号： G03F7/38 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L21/00 ,  H01L21/302 ,  H01L21/461 ,  H01L21/84

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76831

摘要： A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).

摘要翻译： 一种制造具有镶嵌结构的半导体器件的方法包括在衬底上形成第一层间绝缘膜（6）和由低介电常数膜形成的第二层间绝缘膜（4）的工艺，形成通孔（9 ）通过使用形成在第二层间绝缘膜上的第一抗蚀剂图案（1a），使用含有胺成分的有机剥离液进行有机剥离处理，然后在第二层间绝缘膜上形成第二抗蚀剂图案（1b）。 在湿处理之后，涂覆第二抗反射涂层（2b）以便位于第二抗蚀图案下方的涂层，退火处理，等离子体处理，UV处理和有机溶剂处理中的至少一个是 进行以除去抑制在曝光时在抗蚀剂中发生的酸的催化反应的胺成分，从而防止第二抗蚀剂图案（1b）的分辨率的劣化。

公开(公告)号：US06531755B1

公开(公告)日：2003-03-11

申请号：US09686800

申请日：2000-10-12

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L2900

CPC分类号： H01L21/76802 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/31695 ,  H01L21/76826 ,  Y10S257/92

摘要： In a semiconductor device in which an interlayer insulating layer is formed of a low density material (porous silica etc.) and a hole or a trench is formed in the interlayer insulating layer by processing the interlayer insulating layer and an electrically conductive material is coated on the processed surface of the hole or trench for establishing electrical connection, the density of part of the interlayer insulating layer near the processed surface of the hole or trench is increased in comparison with other parts of the interlayer insulating layer. The densification process is conducted by the elimination of microvoids near the processed surface, for example. The densification or the microvoid elimination can be conducted by use of ammonia water, vapor of ammonia water, ammonia plasma treatment, etc. By the densification process, coating of the electrically conductive material (Cu etc.) on the processed surface of the hole or trench can be conducted successfully in the following steps and thereby the manufacture of semiconductor devices of stable performance can be realized. By the use of the low density material for the interlayer insulating layer, the space between wires in the semiconductor device can be made smaller and thereby miniaturization and speeding up of semiconductor device can be attained.

公开(公告)号：US06468898B1

公开(公告)日：2002-10-22

申请号：US09672303

申请日：2000-09-29

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L214763

CPC分类号： H01L21/76811

摘要： In removing individual photoresist films used for forming a via hole and an overlying wiring trench, a low dielectric constant film is prevented from being subjected to a plasma ashing treatment, which makes it possible to produce a good quality dual damascene wiring structure. After formation of a metal mask which is WN film on an interlayer insulation film including the low dielectric constant film, a first photoresist film and a second photoresist film are sequentially formed on the WN film, wherein the first photoresist film and the second photoresist film are patterned to to have patterns for forming a via hole and an overlying wiring trench, respectively; then, the WN film is patterned according to a pattern of each of the first photoresist film and the second photoresist film; and, after that, the interlayer insulation film is patterned using the WN film as a mask to form the via hole and the overlying wiring trench in the interlayer insulation film.

摘要翻译： 在去除用于形成通孔和上覆布线沟槽的单个光致抗蚀剂膜时，防止低介电常数膜经受等离子体灰化处理，这使得可以生产出良好的双色镶嵌布线结构。 在包括低介电常数膜的层间绝缘膜上形成WN膜的金属掩模后，在WN膜上依次形成第一光致抗蚀剂膜和第二光致抗蚀剂膜，其中第一光致抗蚀剂膜和第二光致抗蚀剂膜为 图案化以分别具有用于形成通孔和上覆布线沟槽的图案; 然后，根据第一光致抗蚀剂膜和第二光致抗蚀剂膜的图案，对WN膜进行图案化; 之后，使用WN膜作为掩模对层间绝缘膜进行图案化，以在层间绝缘膜中形成通孔和上覆布线沟槽。

公开(公告)号：US06358808B1

公开(公告)日：2002-03-19

申请号：US09714607

申请日：2000-11-16

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L2120

CPC分类号： H01L27/11 ,  H01L21/3185 ,  H01L27/1112 ,  Y10S257/904

摘要： In a method of manufacturing a semiconductor device, an insulating film is formed on a semiconductor substrate. A semiconductor film pattern is formed on the insulating film. A direct thermal nitriding method is performed to at least a portion of the semiconductor film pattern. The direct thermal nitriding method is performed by lamp annealing in a gas composed of nitrogen such that a thermally nitrided film has a film thickness of equal to or thicker than 1.5 nm. Thus, invasion of a hydrogen atom or ion into the semiconductor film pattern can be prevented.

摘要翻译： 在制造半导体器件的方法中，在半导体衬底上形成绝缘膜。 在绝缘膜上形成半导体膜图形。 对半导体膜图案的至少一部分进行直接热氮化方法。 直接热氮化方法通过在由氮组成的气体中进行灯退火，使得热氮化膜具有等于或大于1.5nm的膜厚度来进行。 因此，可以防止氢原子或离子侵入到半导体膜图案中。

公开(公告)号：US6077574A

公开(公告)日：2000-06-20

申请号：US912468

申请日：1997-08-18

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L21/768 ,  C23C16/40 ,  C23C16/507 ,  C23C16/511 ,  H01L21/314 ,  H01L21/316 ,  H01L23/522 ,  H05H1/24

CPC分类号： H01L21/02274 ,  C23C16/401 ,  C23C16/507 ,  C23C16/511 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/31625

摘要： In a process for forming a plasma CVD fluorine-doped SiO.sub.2 dielectric film, a feed gas to be supplied to a plasma CVD apparatus is composed to include not only SiH.sub.4 gas, O.sub.2 gas, CF.sub.4 gas and Ar gas but also CO.sub.2 gas, and the amount of carbon and the amount of fluorine included in the feed gas are controlled independently of each other, to form a plasma CVD silicon-based SiO.sub.2 dielectric film doped with fluorine in the concentration range of 4.0.times.10.sup.21 atoms/cc to 1.0.times.10.sup.22 atoms/cc, and carbon in the concentration range of 3.0.times.10.sup.19 atoms/cc to 1.0.times.10.sup.21 atoms/cc. Thus, a plasma CVD silicon-based SiO.sub.2 dielectric film having a low dielectric constant and a sufficient "resistance to moisture" is obtained.

摘要翻译： 在形成等离子体CVD氟掺杂的SiO 2电介质膜的方法中，供给到等离子体CVD装置的进料气体不仅包括SiH 4气体，O 2气体，CF 4气体和Ar气体，而且包括CO 2气体， 能够独立地控制进料气体中所含的碳和氟的量，以形成浓度范围为4.0×10 21原子/ cc〜1.0×10 22原子/ cc的氟等离子体CVD硅系Si​​O 2介质膜 ，浓度范围为3.0×1019原子/ cc至1.0×1021原子/ cc的碳。 因此，获得具有低介电常数和足够的“耐湿性”的等离子体CVD硅基SiO 2电介质膜。

公开(公告)号：US08592303B2

公开(公告)日：2013-11-26

申请号：US12715088

申请日：2010-03-01

申请人： Munehiro Tada ,  Yoshihiro Hayashi ,  Yoshimichi Harada ,  Fuminori Ito ,  Hiroto Ohtake ,  Tatsuya Usami

发明人： Munehiro Tada ,  Yoshihiro Hayashi ,  Yoshimichi Harada ,  Fuminori Ito ,  Hiroto Ohtake ,  Tatsuya Usami

IPC分类号： H01L21/4763

CPC分类号： H01L23/53295 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a semiconductor element thereby obtaining connection of the element, no damage to insulation property between the abutting wirings by occurrence of leakage current and no deterioration of insulation resistance property between the abutting wirings are achieved in case that fine metal wiring is formed in a porous insulation film. The insulation barrier layer 413 is formed between an interlayer insulation film and the metal wiring, in the metal wiring structure on the substrate forming the semiconductor element. The insulation barrier layer enables to reduce leakage current between the abutting wirings and to elevate the insulation credibility.

摘要翻译： 提供一种布线结构及其制造方法，其中在形成半导体元件的基板上形成金属布线的多层布线的布线结构中，从而获得元件的连接，不会损坏绝缘性能 在多孔绝缘膜中形成细小的金属布线的情况下，可以通过发生漏电流而在邻接布线之间形成邻接布线之间的绝缘电阻特性。 在形成半导体元件的基板上的金属布线结构中，在层间绝缘膜和金属布线之间形成绝缘阻挡层413。 绝缘阻挡层能够减少邻接布线之间的泄漏电流并提高绝缘可靠性。

公开(公告)号：US07701060B2

公开(公告)日：2010-04-20

申请号：US10558367

申请日：2004-05-28

申请人： Munehiro Tada ,  Yoshihiro Hayashi ,  Yoshimichi Harada ,  Fuminori Ito ,  Hiroto Ohtake ,  Tatsuya Usami

发明人： Munehiro Tada ,  Yoshihiro Hayashi ,  Yoshimichi Harada ,  Fuminori Ito ,  Hiroto Ohtake ,  Tatsuya Usami

IPC分类号： H01L23/48

CPC分类号： H01L23/53295 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a semiconductor element thereby obtaining connection of the element, no damage to insulation property between the abutting wirings by occurrence of leakage current and no deterioration of insulation resistance property between the abutting wirings are achieved in case that fine metal wiring is formed in a porous insulation film. The insulation barrier layer 413 is formed between an interlayer insulation film and the metal wiring, in the metal wiring structure on the substrate forming the semiconductor element. The insulation barrier layer enables to reduce leakage current between the abutting wirings and to elevate the insulation credibility.

摘要翻译： 提供一种布线结构及其制造方法，其中在形成半导体元件的基板上形成金属布线的多层布线的布线结构中，从而获得元件的连接，不会损坏绝缘性能 在多孔绝缘膜中形成细小的金属布线的情况下，可以通过发生漏电流而在邻接布线之间形成邻接布线之间的绝缘电阻特性。 在形成半导体元件的基板上的金属布线结构中，在层间绝缘膜和金属布线之间形成绝缘阻挡层413。 绝缘阻挡层能够减少邻接布线之间的泄漏电流并提高绝缘可靠性。

公开(公告)号：US07687917B2

公开(公告)日：2010-03-30

申请号：US10650193

申请日：2003-08-28

申请人： Koichi Ohto ,  Toshiyuki Takewaki ,  Tatsuya Usami ,  Nobuyuki Yamanishi

发明人： Koichi Ohto ,  Toshiyuki Takewaki ,  Tatsuya Usami ,  Nobuyuki Yamanishi

IPC分类号： H01L23/48

CPC分类号： H01L21/022 ,  H01L21/02074 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3124 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.

摘要翻译： 在半导体器件中，在绝缘底层上形成具有凹槽的绝缘中间层。 不含金属硅化物的硅扩散金属层埋入槽内。 在硅扩散金属层和绝缘中间层上形成金属扩散阻挡层。