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公开(公告)号:US12255062B2
公开(公告)日:2025-03-18
申请号:US18509053
申请日:2023-11-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Xin-Hua Huang , Ping-Yin Liu , Hung-Hua Lin , Hsun-Chung Kuang , Yuan-Chih Hsieh , Lan-Lin Chao , Chia-Shiung Tsai , Xiaomeng Chen
IPC: B23K1/00 , B23K1/20 , B23K20/02 , B23K20/233 , B23K20/24 , H01L21/00 , H01L21/02 , H01L23/00 , B23K101/40 , B23K101/42
Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
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公开(公告)号:US20220208607A1
公开(公告)日:2022-06-30
申请号:US17697557
申请日:2022-03-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Hsun-Chung Kuang , Yen-Chang Chu , Cheng-Tai Hsiao , Ping-Yin Liu , Lan-Lin Chao , Yeur-Luen Tu , Chia-Shiung Tsai , Xiaomeng Chen
IPC: H01L21/768 , H01L23/00 , H01L23/31 , H01L25/04 , H01L25/075 , H01L23/538 , H01L25/065 , H01L23/29 , H01L25/00
Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
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公开(公告)号:US20210151353A1
公开(公告)日:2021-05-20
申请号:US17140794
申请日:2021-01-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Hsun-Chung Kuang , Yen-Chang Chu , Cheng-Tai Hsiao , Ping-Yin Liu , Lan-Lin Chao , Yeur-Luen Tu , Chia-Shiung Tsai , Xiaomeng Chen
IPC: H01L21/768 , H01L23/00 , H01L23/31 , H01L25/04 , H01L25/075 , H01L23/538 , H01L25/065 , H01L23/29 , H01L25/00
Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
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公开(公告)号:US09708179B2
公开(公告)日:2017-07-18
申请号:US14967663
申请日:2015-12-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yuan-Chih Hsieh , Li-Cheng Chu , Hung-Hua Lin , Chih-Jen Chan , Lan-Lin Chao
IPC: H01L23/12 , B81B7/00 , B81C1/00 , H01L23/26 , H01L21/322
CPC classification number: B81B7/0038 , B81B7/0025 , B81B2201/0235 , B81B2201/0242 , B81B2203/0315 , B81C1/00285 , B81C2203/0118 , H01L21/3223 , H01L23/26 , H01L2924/0002 , H01L2924/00
Abstract: In some embodiments, the present disclosure relates to a MEMs (microelectromechanical system) package device having a getter layer. The MEMs package includes a first substrate having a cavity located within an upper surface of the first substrate. The cavity has roughened interior surfaces. A getter layer is arranged onto the roughened interior surfaces of the cavity. A bonding layer is arranged on the upper surface of the first substrate on opposing sides of the cavity, and a second substrate bonded to the first substrate by the bonding layer. The second substrate is arranged over the cavity. The roughened interior surfaces of the cavity enables more effective absorption of residual gases, thereby increasing the efficiency of a gettering process.
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