公开(公告)号：US20210249421A1

公开(公告)日：2021-08-12

申请号：US16786099

申请日：2020-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chiung-Ting OU ,  Ming-Yih WANG ,  Jian-Hong LIN

IPC: H01L27/112 ,  H01L23/48

Abstract: A memory device includes a transistor, an anti-fuse element, a gate via, and a bit line. The transistor includes two source/drain regions. The anti-fuse element is connected to one of the source/drain regions of the transistor. The anti-fuse element includes a channel and a gate structure above the channel. The gate via is above the gate structure of the anti-fuse element. A lateral distance between a center of the gate via and a sidewall of the channel is less than a width of the gate via. The bit line is connected to another of the source/drain regions of the transistor.

公开(公告)号：US20180269148A1

公开(公告)日：2018-09-20

申请号：US15463105

申请日：2017-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Hong LIN ,  Hsin-Chun CHANG ,  Hui LEE ,  Yung-Sheng HUANG ,  Yung-Huei LEE

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  G06F17/50

CPC classification number: H01L23/5226 ,  G06F17/5077 ,  H01L23/5283 ,  H01L27/0207

Abstract: A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.

公开(公告)号：US20170053865A1

公开(公告)日：2017-02-23

申请号：US14832055

申请日：2015-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Jian-Hong LIN ,  Chwei-Ching CHIU ,  Yung-Huei LEE ,  Chien-Neng LIAO ,  Yu-Lun CHUEH ,  Tsung-Cheng CHAN ,  Chun-Lung HUANG

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/288 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: A semiconductor device structure with twin-boundaries and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive structure formed over the substrate. The conductive structure includes twin boundaries, and a density of the twin boundaries is in a range from about 25 μm−1 to about 250 μm−1.

Abstract translation: 提供了具有双边界的半导体器件结构及其形成方法。 半导体器件结构包括衬底和形成在衬底上的导电结构。 导电结构包括双边界，并且双边界的密度在约25μm-1至约250μm-1的范围内。