公开(公告)号：US12157667B2

公开(公告)日：2024-12-03

申请号：US17719986

申请日：2022-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chun Weng ,  Lavanya Sanagavarapu ,  Ching-Hsiang Hu ,  Wei-Ding Wu ,  Shyh-Wei Cheng ,  Ji-Hong Chiang ,  Hsin-Yu Chen ,  Hsi-Cheng Hsu

IPC: B81B3/00 ,  B81C1/00 ,  H01J37/34 ,  H01L21/02

Abstract: A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.

公开(公告)号：US11454820B2

公开(公告)日：2022-09-27

申请号：US16656290

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yu Chen ,  Yen-Chiang Liu ,  Jiun-Jie Chiou ,  Jia-Syuan Li ,  You-Cheng Jhang ,  Shin-Hua Chen ,  Lavanya Sanagavarapu ,  Han-Zong Pan ,  Chun-Peng Li ,  Chia-Chun Hung ,  Ching-Hsiang Hu ,  Wei-Ding Wu ,  Jui-Chun Weng ,  Ji-Hong Chiang ,  Hsi-Cheng Hsu

IPC: G02B27/30 ,  G02B5/20 ,  G02B26/00 ,  H01L27/146 ,  H01L31/0216 ,  G06V40/13

Abstract: Disclosed is a cost-effective method to fabricate a multifunctional collimator structure for contact image sensors to filter ambient infrared light to reduce noises. In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; a plurality of via holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction.

公开(公告)号：US11407636B2

公开(公告)日：2022-08-09

申请号：US16122180

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Wei Cheng ,  Chih-Yu Wang ,  Hsi-Cheng Hsu ,  Ji-Hong Chiang ,  Jui-Chun Weng ,  Shiuan-Jeng Lin ,  Wei-Ding Wu ,  Ching-Hsiang Hu

IPC: B81B7/00 ,  B81C1/00

Abstract: The present disclosure, in some embodiments, relates to a method of forming a micro-electromechanical system (MEMS) package. The method includes forming one or more depressions within a capping substrate. A back-side of a MEMS substrate is bonded to the capping substrate after forming the one or more depressions, so that the one or more depressions define one or more cavities between the capping substrate and the MEMS substrate. A front-side of the MEMS substrate is selectively etched to form one or more trenches extending through the MEMS substrate, and one or more polysilicon vias are formed within the one or more trenches. A conductive bonding structure is formed on the front-side of the MEMS substrate at a location contacting the one or more polysilicon vias. The MEMS substrate is bonded to a CMOS substrate having one or more semiconductor devices by way of the conductive bonding structure.

公开(公告)号：US11305980B2

公开(公告)日：2022-04-19

申请号：US16717862

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chun Weng ,  Lavanya Sanagavarapu ,  Ching-Hsiang Hu ,  Wei-Ding Wu ,  Shyh-Wei Cheng ,  Ji-Hong Chiang ,  Hsin-Yu Chen ,  Hsi-Cheng Hsu

IPC: B81B3/00 ,  H01J37/34 ,  B81C1/00 ,  H01L21/02

Abstract: A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.

公开(公告)号：US09884758B2

公开(公告)日：2018-02-06

申请号：US15182754

申请日：2016-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Wei Cheng ,  Hsi-Cheng Hsu ,  Hsin-Yu Chen ,  Ji-Hong Chiang ,  Jui-Chun Weng ,  Wei-Ding Wu ,  Yu-Jui Wu ,  Ching-Hsiang Hu ,  Ming-Tsung Chen

IPC: H01L21/00 ,  B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00285 ,  B81B7/0038 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2207/012 ,  B81B2207/07 ,  B81C2203/0118 ,  B81C2203/0792

Abstract: The present disclosure relates to a MEMS package having an outgassing element configured to adjust a pressure within a hermetically sealed cavity by inducing outgassing of into the cavity, and an associated method. In some embodiments, the method is performed by forming an outgassing element within a passivation layer over a CMOS substrate and forming an outgassing resistive layer to cover the outgassing element. The outgassing resistive layer is removed from over the outgassing element, and the MEMS substrate is bonded to a front side of the CMOS substrate to enclose a first MEMS device within a first cavity and a second MEMS device within a second cavity. After removing the outgassing resistive layer, the outgassing element releases a gas into the second cavity to increase a second pressure of the second cavity to be greater than a first pressure of the first cavity.

公开(公告)号：US20170107097A1

公开(公告)日：2017-04-20

申请号：US14980297

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Wei Cheng ,  Chih-Yu Wang ,  Hsi-Cheng Hsu ,  Ji-Hong Chiang ,  Jui-Chun Weng ,  Shiuan-Jeng Lin ,  Wei-Ding Wu ,  Ching-Hsiang Hu

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B7/0006 ,  B81B2207/012 ,  B81B2207/096 ,  B81C1/00238 ,  B81C1/00301 ,  B81C2201/013 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/037 ,  B81C2203/0792

Abstract: The present disclosure relates to micro-electromechanical system (MEMS) package that uses polysilicon inter-tier connections to provide for a low parasitic capacitance in MEM device signals, and a method of formation. In some embodiments, the MEMS package has a CMOS substrate with one or more semiconductor devices arranged within a semiconductor body. A MEMS substrate having an ambulatory element is connected to the CMOS substrate by a conductive bonding structure. The conductive bonding structure is arranged on a front-side of the MEMS substrate at a location laterally offset from the ambulatory element. One or more polysilicon vias extend through the conductive MEMS substrate to the bonding structure. The one or more polysilicon vias are configured to electrically couple the MEMS substrate to the CMOS substrate. By connecting the MEMS substrate to the CMOS substrate using the polysilicon vias, the parasitic capacitance and form factor of the MEMS package are reduced.