公开(公告)号：US20200020644A1

公开(公告)日：2020-01-16

申请号：US16043355

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Yu LEE ,  Chin-Chou Liu ,  Cheng-Hung Yeh ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Ka Fai Chang

IPC: H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  G06F17/50 ,  H01L23/522

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

公开(公告)号：US09330215B2

公开(公告)日：2016-05-03

申请号：US14219029

申请日：2014-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Hsien Tsai ,  Chi-Ting Huang ,  Cheng-Hung Yeh ,  Hsien-Hsin Sean Lee

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/504 ,  G06F17/5081 ,  G06F2217/82

Abstract: A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic (“LVS”) check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.

Abstract translation: 一种用于验证具有多个层的IC的设计的方法包括进行布局与示意图（“LVS”）检查以分离多个设计布局中的多个设备，其中每个设计布局对应于具有 各自的设备。 使用计算设备在彼此的不同层中的一个设备之间生成多个相邻层连接。 执行每个层的第一RC提取以计算相应设计布局的多个设备中的每一个之间的耦合。 执行每个相邻层连接的第二RC提取。